Method for fabricating semiconductor circuits
AssigneeSGS-Thomson Microelectronics S.A.
InventorsTsiu C. Chan, William A. Bishop
Life of this patent
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Abstract
A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.
Claims7
A method for forming an interconnect in an integrated circuit device, comprising the steps of:
- forming a patterned first layer of polycrystalline silicon over the device defining a first layer of conductive elements;
- forming an insulating layer over the patterned first polycrystalline silicon layer, wherein sidewalls are produced where the insulating layer passes over the first level polycrystalline silicon layer;
- forming a second layer of polycrystalline silicon over the insulating layer;
- defining a pattern for the second polycrystalline silicon layer to define a second layer of conductive elements, wherein, for each first layer conductive element, all second layer conductive elements that cross over such first layer conductive element are connected to a common electrical node in order for these second layer conductive elements to have the same voltage during device operation;
- etching the second polycrystalline silicon layer using the defined pattern;
- and
- leaving behind a second level polycrystalline silicon stick along the sidewall of the insulating layer after etching the second polycrystalline silicon layer;
- wherein current flow through the second level polycrystalline silicon stick is prevented during device operation.
A method for forming a shared contact in an integrated circuit device, comprising the steps of:
- forming a conductive region in a substrate;
- forming a first insulating layer over the substrate;
- forming a patterned first polycrystalline silicon layer over the first insulating layer, said patterned first polycrystalline silicon layer defining first layer conductive elements;
- forming a second insulating layer over the first insulating layer and the patterned first polycrystalline layer;
- forming an opening through the second insulating layer and the first insulating layer to expose the conductive region, wherein a portion of a first layer conductive element is exposed in the opening;
- depositing a second polycrystalline silicon layer over the second insulating layer and in the opening, wherein the second polycrystalline silicon layer contacts the conductive region;
- and
- patterning the second polycrystalline layer to define second layer conductive elements, wherein a second layer conductive element contacts both the exposed conductive region and the exposed first layer conductive element portion;
- wherein the step of forming a patterned first polycrystalline silicon layer comprises the step of forming first layer conductive elements which are gate electrodes for field effect transistors.
A method for forming interconnect in an integrated circuit device, comprising the steps of:
- forming a patterned first layer of polycrystalline silicon over the device defining a first layer of conductive elements;
- forming an insulating layer over the patterned first polycrystalline silicon layer;
- forming a second layer of polycrystalline silicon over the insulating layer;
- defining a pattern for the second polycrystalline silicon layer to define a second layer of conductive elements, wherein, for each first layer conductive element, all second layer conductive elements which cross over such first layer conductive elements are connected to a common electrical node in order for these second layer conductive elements to have the same voltage during device operation;
- and
- etching the second polycrystalline silicon layer using the defined pattern;
- wherein the step of forming a patterned first polycrystalline silicon layer comprises the step of forming first layer conductive elements which are gate electrodes for field effect transistors.
Dependencies are inferred from the claim text.