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US 5,329,633 AGranted
Cache memory system, and comparator and MOS analog XOR amplifier for use in the system
AssigneeAcer Incorporated
InventorsSheau-Jiung Lee, Gene Yang
Life of this patent
Estimating the term…
Abstract
The MOS analog multi-bit comparator amplifier for performing the high speed digital multi-bit comparator function which is required, for example, in Cache Tag Random Access Memory of a computer system, and to the MOS analog XOR amplifier for performing the digital XOR function. The MOS analog comparator provided comprises N number of MOS analog XOR means for performing the digital XOR function and a MOS analog NOR means for performing the digital NOR function.
Claims20
A Tag random access memory (RAM) device for use in a cache Tag RAM of a computer system with N-bit address lines, said memory device comprising:
- a Tag static RAM having N bits data output;
- a metal oxide semiconductor (MOS) comparator for comparing the N bits data output of said static RAM with said N bits address line of said computer system, said comparator including:
- (a) N number of MOS analog exclusive-OR (XOR) means each having an input connected to one bit of address lines of said computer system and having a reference input connected to one bit of said data output of said Tag static RAM for XOR comparison with one bit of said address lines;
- (b) a MOS not-OR (NOR) means having N input gate terminals each connected to one output of said analog XOR means, said NOR means outputting a logic "1" state when every bit of address lines of said computer system is identical with a corresponding bit of data output of said Tag RAM and outputting a logic "0" state when at least one bit of address lines of said computer system is not identical with said corresponding bit of data output of said Tag RAM;
- The MOS analog NOR means including:
- a constant current source;
- first and second load means;
- a reference MOS transistor having its source terminal connected to said constant current source, its gate terminal connected to a constant reference voltage and drain terminal connected to the first load means;
- and
- N number of input MOS transistors, the source terminal of each of said input MOS transistors being connected to said constant current source and the drain terminal of each of said input MOS transistors being connected to the second load means, for forming a MOS analog NOR amplifier, wherein drain terminals of said input MOS transistors generate a first output voltage at a node common to said drain terminals of said input MOS transistors and the drain terminal of said reference MOS transistor generates a second output voltage, so that when a logic "0" signal is applied to the input gate terminal of each of said input MOS transistors, the first output voltage is higher than the second output voltage, representing a HIT status, and so that when at least one logic "1" signal is applied to the input gate terminal of at least one input MOS transistor, the second output voltage is higher than the first output voltage, representing a MISS status.
7 more elements
A Tag random access memory (RAM) device for use in a cache memory of a computer system with N-bit address lines, said Tag RAM device comprising:
- a Tag static RAM having N bits data output;
- a metal oxide semiconductor (MOS) comparator for comparing the N bits data output of said static RAM with said N bits address line of said computer system, said comparator including:
- (a) N number of MOS analog exclusive-OR (XOR) means each having an input connected to one bit of address lines of said computer system and having a reference input connected to one bit of said data output of said Tag static RAM for XOR comparison with one bit of said address lines;
- (b) a MOS not-OR (NOR) means having N input gate terminals each connected to one output of said analog XOR means, said NOR means outputting a logic "1" state when every bit of address lines of said computer system is identical with a corresponding bit of data output of said Tag RAM and outputting a logic "0" state when at least one bit of address lines of said computer system is not identical with said corresponding bit of data output of said Tag RAM;
- wherein the MOS analog XOR means has a first and a second output, said analog XOR means including:
- a constant current source;
- a first MOS switch having a source terminal connected to said constant current source, a gate terminal connected to said one bit of said address lines of said computer system;
- a first MOS differential pair having a first and a second input MOS transistors whose source terminals being commonly connected to a drain terminal of said first MOS switch;
- a second MOS switch having a source terminal connected to the source terminal of said first MOS switch, a second gate terminal connected to complementary signal of said one bit of said address lines of said computer system;
- a second MOS differential pair having a third and a fourth input MOS transistors whose source terminals being commonly connected to a drain terminal of said second MOS switch;
- wherein drain terminals of the first and third input MOS transistors are connected to the first output of the analog XOR means, and drain terminals of the second and fourth input MOS transistors are connected to the second output of the analog XOR means, and wherein said one bit of said data output of said Tag static RAM is represented by two different signal values, each of said two signal values being applied to a gate terminal of one of the transistors of each differential pair in order to compare said one bit of said address lines with said one bit of said data output.
8 more elements
A Tag random access memory (RAM) device for use in a cache memory of a computer system with N-bit address line, said Tag RAM device comprising:
- a Tag static RAM having N bits data output;
- and
- a metal oxide semiconductor (MOS) comparator for comparing the N bits data output of said static RAM with said N bits address line of said computer system, said comparator including:
- (a) N number of MOS analog exclusive-OR (XOR) means each having an input connected to one bit of address lines of said computer system and having a reference input connected to one bit of said data output of said Tag static RAM for XOR comparison with one bit of said address lines, wherein each of said XOR means includes a plurality of interconnected transistors in a constantly on state;
- (b) a MOS not-OR (NOR) means having N input gate terminals each connected to one output of said analog XOR means, said NOR means outputting a logic "1" state when every bit of address lines of said computer system is identical with a corresponding bit of data output of said Tag RAM and outputting a logic "0" state when at least one bit of address lines of said computer system is not identical with said corresponding bit of data output of said Tag RAM.
2 more elements
Dependencies are inferred from the claim text.