System and method using double-buffer preview mode

A system comprising:

• a first processor and a second processor, connected and programmed to operate concurrently and asynchronously;
• a subsystem for double buffering, which includes:
• first and second interface ports;
• a dual port memory connected to be accessible through said first and second ports and which comprises first and second parts;
• and a memory access controller, which
• maintains an allocation of two parts of said memory between said interface ports, and
• is connected to receive a mode signal, and
• is connected and configured to arbitrate access to two parts of said memory from said interface ports, in accordance with said allocation and with the mode selected by said mode signal, such that:
• when a first mode has been selected by said mode signal, any part of said memory may be read or written to by either of said ports, regardless of said allocation;
• and
• when a second mode has been selected by said mode signal, each said port can read or write to only the respective part of said memory defined by said allocation;
• and
• when a third mode has been selected by said mode signal, said memory access controller arbitrates access to said two parts of said memory from said interface ports such that each said port can read the opposite part of said memory, which said allocation has assigned to the other respective one of said ports;
• and
• wherein said memory controller is connected to arbitrate access to said first and second ports between said first and second processors, and is connected to receive one or more bank-switch signals from one or more of said processors and alter said allocation accordingly.

A method of using a computer system which includes first and second processors corrected and programmed to operate concurrently and asynchronously, comprising the steps of:

• providing a dual-port memory having first and second parts, a memory access controller which is connected to arbitrate access to said first and second parts of said dual-port memory between said first and second processors, and which maintains an allocation of two parts of said dual-port memory between said processors, and which is connected to receive a mode signal, and which is connected to receive one or more bank-switch signals, and which is connected to receive access requests from said processors, and which arbitrates access by said processors to said two parts of said memory, in accordance with the mode selected by said mode signal and in accordance with the allocation, such that:
• when a first mode has been selected by said mode signal, any part of said memory may be read or written to by either of said processors, regardless of said allocation;
• and when a second mode has been selected by said mode signal, each said processor can read or write to only the respective part of said memory defined by said allocation;
• and when a third mode has been selected by said mode signal, such that each said port can read the opposite part of said memory, which said allocation has assigned to the other said port;
• providing a multiprocessing program which includes synchronization points;
• providing input data to be operated on in accordance with steps of said program;
• executing a first set of steps of the program on said first processor, and concurrently, executing a second set of steps of the program on said second processor, data inputs and outputs of said processors being connected to provide a pipelined data flow;
• operating said access controller primarily in said second mode thereof, so that said first processor reads and writes primarily to said first part of said memory and said second processor reads and writes primarily to said second part;
• and, when both said processors have reached respective synchronization points in said respective program steps, reversing said allocation of said parts of said address space between said first and second processors;
• wherein, prior to said step of reversing the assignment, at least said first processor reads at least some data from said memory in said third mode;
• and
• providing an output corresponding to the results of said program steps on said input data.

A subsystem for double buffering, comprising:

• first and second interface ports;
• a dual port memory which comprises first and second parts and which is accessible to said first and second ports;
• a memory access controller, which
• is connected to receive one or more bank-switch request signals, and maintains an allocation of said two parts of said memory between said interface ports, and conditionally changes said allocation in accordance with said bank-switch signals, and
• is connected to receive a mode signal, and
• is connected and configured to arbitrate access to two parts of said memory from said interface ports, in accordance with the mode selected by said mode signal, such that:
• when a first mode has been selected by said mode signal, any part of said memory may be read or written to by either of said ports, regardless of said allocation;
• when a second mode has been selected by said mode signal, each said port can read or write to only the respective part of said memory defined by said allocation;
• when a third mode has been selected by said mode signal, said memory access controller arbitrates access to said two parts of said memory from said interface ports such that each said port can read the opposite part of said memory, which said allocation has assigned to the other respective one of said ports.