Apparatus and method for reading, writing, and refreshing memory with direct virtual or physical access

A memory system for accessing memory elements in an array having a first plurality of memory elements in response to a sequential plurality of memory address requests, at least one of said memory address requests having a correspondence with at least one of said first plurality of memory elements, comprising:

• an array of memory elements, each element having an address comprising a first number of row address bits and a second number of column address bits;
• first address register means for holding a third number of column address bits for use in accessing a memory element having an address which includes said third number of column bits, said third number being less than said second number;
• second means, using a fourth number of column address bits, for use in accessing a memory element having an address which includes said fourth number of column address bits, said fourth number being less than said second number;
• third means for providing a number of bits from each of said sequential plurality of memory address requests to said first address register, said provided number being equal to said third number;
• fourth means for continuously maintaining said fourth number of column bits in said second means during at least two of said sequential plurality of memory address requests;
• and
• fifth means for accessing at least one of said first plurality of memory elements using said third number of column address bits in said first address register means, and said fourth number of column address bits in said second means.

A computer memory system comprising:

• a fast page random access column- and row-organized memory, including first, second, third, and fourth address latches, each row latch for holding an address indicating one row of said memory so that the contents of memory in said row can be rapidly accessed by strobing a CAS signal, said row being specifiable by a row address, each element in said memory array having an address comprising at least 10 row address bits and at least 10 column address bits;
• a first address register for holding at least eight column address bits usable in accessing a memory element in a row indicated by one of said row address latches;
• a first means for holding at least two column address bits usable in accessing a memory element in at least one of said row address latches;
• a memory request register for holding bits comprising the requested addresses of a sequential plurality of requested memory elements, wherein said requested addresses are selected from the group consisting of physical addresses and virtual addresses;
• means for providing eight column address bits from each of said sequential plurality of memory address requests in said memory request register to said first address register;
• first, second, third, and fourth virtual/physical row address registers for holding a row address corresponding to the row held by said first, second, third, and fourth row address latches, respectively, said row address selected from the group consisting of a physical address and a virtual address;
• first, second, third, and fourth physical address registers, each physical address register holding a physical row address corresponding to the row indicated by said first, second, third, and fourth row address latches, respectively, and also holding at least two column address bits corresponding to a column address usable in accessing a memory element having a column address which includes said two column address bits;
• a comparator for comparing at least a first plurality of bits from an address in said memory request register to the contents of each of said first, second, third, and fourth virtual/physical address registers, and for generating a first signal when the contents of at least one of said first, second, third, or fourth virtual/physical address registers is identical to said first plurality of bits, and for generating a second signal when the contents of none of said first, second, third, or fourth virtual/physical address registers are identical to said first plurality of bits;
• third means for continuously maintaining said two column bits in said first means during at least two of said plurality of memory address requests, until said second signal is generated;
• fourth means for changing the contents of at least one of said first, second, third or fourth row address latches following generation of said second signal;
• and
• fifth means for determining whether said memory request address is a virtual address or a physical address, and for setting at least one bit in said memory request register to indicate whether said memory request address is a virtual address or a physical address.

Apparatus for translating at least one of a plurality of virtual addresses to a corresponding physical address, comprising:

• a first table having a plurality of entries, each entry containing data for translating a virtual address to a physical address;
• a second table containing a plurality of entries;
• means for making a corresponding change to said second table whenever there is a change made to said first table, wherein said second table is substantially identical to said first table;
• means for detecting an error condition in said first table;
• means for translating a virtual address to a physical address using only said first table, and without using said second table, during a period when no errors have been detected by said means for detecting an error;
• and
• means for selecting said second table for use by said means for translating and for discontinuing use of said first table when an error condition is detected by said means for detecting.

A method for accessing memory, comprising:

• providing a fast page dynamic random access memory array having at least one row address latch;
• providing at least a first virtual/physical address register for holding at least a portion of a row address corresponding to a row held by at least a first row address latch wherein the contents of said first virtual/physical address register comprises at least portions of a virtual address during a first time period and at least portions of a physical address, different from said virtual address, during a second time period said second time period being different from said first time period;
• comparing at least some selected bits from a memory request address with the contents of said virtual/physical address register, generating a first signal when said selected bits are identical, and generating a second signal when said selected bits are not identical wherein said memory request address comprises one of a plurality of virtual or physical address requests and wherein said comparing comprises comparing said at least some selected bits from said memory request address to the contents of said virtual/physical address register when said one of said plurality of virtual or physical address requests is a virtual address request and wherein said comparing comprises comparing said at least some selected bits from said memory request address to the contents of said virtual/physical address register when said one of said plurality of virtual or physical address request is a physical address request. ;
• and
• asserting a column address strobe to said row address latch following said first signal.

A method for sequentially accessing a plurality of memory elements in a memory array in response to a sequential plurality of memory address requests, comprising:

• providing an array of memory elements, each element having an address comprising a first number of row bits and a second number of column bits;
• providing first address register means for holding a third number of column address bits for use in accessing a memory element having an address which includes said third number of column address bits, said third number being less than said second number;
• providing second means, using a fourth number of column address bits, for use in accessing a memory element having an address which includes said fourth number of column address bits, said fourth number being less than said second number;
• transmitting a number of bits from each of said sequential plurality of memory address requests to said first address register, said number of transmitted bits being equal to said third number;
• continuously maintaining said fourth number of column address bits in said means during at least two of said plurality of memory address requests;
• and
• accessing a memory element using said third number of bits in said first address register means and said fourth number of bits in said second means.