Concurrent general purpose and DMA processing in a graphics rendering processor

A display system for comprising:

• a graphics processor for generating graphic pixel signals in response to display lists;
• at least one stored program computer for generating a plurality of display lists, each display list including a plurality of graphic instructions, said plurality of display lists including high priority display lists requiring nearly immediate transfer of said plurality of graphical instructions to said graphics processor and low priority display lists requiring less nearly immediate transfer of said plurality of graphical instructions to said graphics processor;
• a high priority hardware channel and a low priority hardware channel for providing said high priority display lists and said low priority display lists, respectively from said at least one stored program computer to said graphics processor;
• First In First Out (FIFO) controller means coupled to said high priority hardware channel and said low priority hardware channel for receiving and storing said high priority and low priority display lists and coupling said display lists to said graphics processor;
• and
• a display list processing means, said display list processing means receiving said high and low priority display lists from said FIFO controller means, said display list processor including means for processing said high priority display lists before said low priority display lists, said plurality of instructions being received sequentially, said display list processing means having means for concurrently transferring earlier-received instructions of said plurality of instructions of a display list to the graphics processor at the same time that said display list processing means is receiving additional received instructions of said display list from said FIFO controller means.