Scalable flow virtual learning neurocomputer

A neural synapse processor apparatus comprising a neural network emulation structure including:

• partitioned groups comprised of at least one synapse processing unit including means for storing instructions and data, means for receiving instructions and data, means for executing instructions, means for interfacing with external storage units to communicate weights and neuron output values, means for executing group instructions, and communicating adder trees;
• neuron activation units;
• means for interconnecting the groups into a N physical neuron structure supporting the emulation of V neurons (virtual neurons), where N and V are positive integers and V is greater than or equal to N;
• and
• means for communicating instructions, data, and outputs of the neuron activation units back to the synapse processing units through the communicating adder trees;
• the synapse processing units each associated with a connection weight in a neutral network, the neural network in the form of a N by N matrix folded along a diagonal, including diagonal cells and general cells, each of the diagonal cells including one of the synapse processing units and each of the general cells including two of the synapse processing units.

A neural synapse processor apparatus comprising:

• N.sup.2 synapse processing units;
• N communicating adder trees;
• a programmable processor controller;
• and
• N neuron activation units for a N physical neuron structure partitioned into G groups of H synapse processing units per group, each said group interfacing with means for external storage for providing storage capabilities for V virtual neurons, where V is greater than N, with N external summation switching mechanisms, where G, H, V, and N are positive integers.