AGC circuit with non-linear gain for use in PLL circuit

A PLL circuit for generating drive signals to control the speed of a motor according to a reference frequency signal, comprising:

• a circuit for generating a speed signal of frequency proportional to the speed of the motor;
• a phase detector connected to receive the speed signal for producing a signal of duration proportional to a phase difference between the speed signal and the reference frequency signal;
• a phase difference measuring circuit comprising first and second digital up/down counters for:
• (a) producing a first output signal at a first gain proportional to said phase difference when said duration of said phase detector signal is less than a predetermined time, and (b) producing a second output signal at a second gain less than said first gain when said duration of said phase detector signal is greater than said predetermined time;
• a node to which said first and second output signals are applied and summed to produce a summed signal;
• and a motor driver circuit to which said summed signal is applied for controlling the speed of the motor.

A circuit for automatically controlling the gain applied to a signal for driving a motor in a phase-locked loop circuit, having a low gain during convergence and a high gain when a lock range has been reached, comprising:

• frequency detection circuitry for comparing the frequency of a first input signal representing a speed of the motor and the frequency of a second input signal of a reference frequency and emitting a detector output pulse having a duration representing the difference therebetween;
• a plurality of digital counters, each for counting clock pulses during respective successive intervals in the duration of said detector output pulse;
• a plurality of clock signal generators for clocking a respective one of said counters, each of said clock signal generators generating a clock signal having a frequency proportional to a desired counting circuit output gain;
• said counters being connected to count only after saturation of a counter operative during a previous time interval of said detector output pulse, and said clock signals applied to each respective counter that is operative during later intervals being of decreasing frequencies, whereby a discontinuous gain transfer function is produced;
• circuitry for converting the binary numbers generated by the counting circuits to analog output voltages;
• and
• circuitry for summing said analog output voltages for delivery to drive the motor.

A method for generating a drive signal, comprising:

• generating a pulse of length proportional to a phase difference between a reference signal and a resultant signal controlled by said drive signal to which the drive signal is to be synchronized, said resultant signal being derived from a motor speed signal;
• generating a first voltage control signal at a first gain, said first voltage control signal operative within a first range of phase difference between the resultant signal and a reference signal;
• generating a second voltage control signal at a second gain lower than said first gain, said second voltage control signal operative within a second range of phase difference between the resultant signal and a reference signal larger than said first range of phase difference;
• said steps of generating first and second voltage control signals comprising counting first and second clock pulses of different frequencies, and generating said first and second voltage control signals from the respective counts;
• weighting said first and second voltage control signals to produce weighted first and second voltage control signals;
• summing said first and second weighted voltage control signals;
• and
• modifying said drive signal in accordance with said summed first and second weighted voltage control signals.