Decimation filter for a sigma-delta converter and data circuit terminating equipment including the same

A decimation filter for converting an input train of sigma-delta pulses that includes a sigma-delta clock (fs) in synchronism with the sigma-delta clock into a train of Pulse Code Modulation (PCM) samples that include a PCM clock in accordance with the formula ##EQU12## wherein N is the decimation factor, f the frequency and p an integer, said filter comprising means for computing on PCM sample from a sequence of L sigma-delta samples in synchronism with the PCM clock,

• characterized in that it further includes:
• means for determining whether a phase correction has to be introduced in said PCM in order to lock the generation of the PCM samples on the sigma-delta clock extracted from the train of sigma-delta pulses, and
• means responsive to said determination for shifting the computation process of said sequence by at least one sigma-delta clock pulse in order to provide phase control in the generation of the train of PCM samples.