Variable block lengths on-the-fly error correcting decoder

An ECC decoder used with variable block lengths of Reed-Solomon (RS) code for on-the-fly detecting of multiple errors and correction of one error byte per interleave in data recorded on a storage medium in blocks, each data block including variable length data subblocks equal to N*L where N equals a variable number of bytes per interleave and L equals the interleave degree, said ECC decoder comprising:

• delay register means for sequentially receiving consecutive N*L data bytes of said data subblocks at a delay register data input and for sequentially transferring said consecutive N*L data bytes of said data subblocks to a delay register data output;
• each data subblock containing a predetermined number of error check bytes M;
• a plurality M of partial syndrome generator means for sequentially receiving consecutive subblocks of data and generating partial syndromes;
• compare means for comparing said generated partial syndromes to identify agreement;
• and
• a first one of said plurality M of partial syndrome generator means coupled to said delay register data output for selectively adding an error pattern to a transferred data subblock responsive to identified agreement by said compare means;
• and
• wherein said each of said plurality M of partial syndrome generator means includes a first register ring and a second register ring, said first and second register rings including L registers, and wherein said delay register means transfers out consecutive N*L data bytes of said data subblocks at said delay register data output simultaneous with said second register ring.