US 5,329,533 A · Partial-scan built-in self-test technique

Abstract

Testing of an integrated circuit (10), configured of a plurality of flip-flops (14.sub.1 -14.sub.n), at least a portion of which are arranged in a scan chain (16.sub.1 -16.sub.k), is carried out by replacing each self-looping, non-scan chain flip-flop (14.sub.6) with an initializable non-scan flip-flop (64). The integrated circuit (10), including each initializable flip-flop (64) therein, is then initialized prior to placing the integrated circuit in a non-operational mode. During the non-operational mode, a first test vector is shifted through the scan chain flip-flops, causing each to shift out a bit previously latched therein. The integrated circuit (10) is then returned to an operational mode, after which time, a second test vector is applied to its inputs, causing a response to appear at its outputs, and also causing a bit to be shifted into each scan chain flip-flop. The response of the integrated circuit is compacted with the bits shifted from the scan chain flip-flops. By repeating this process for a predetermined number of cycles, a very high indication of the faults in the circuit can be had.

Claims11

Dependent claims

A method for testing an integrated circuit containing a plurality of flip-flops, a selected group of which is arranged in a scan chain for effectuating partial-scan testing of the integrated circuit, the method comprising the steps of:

(a) replacing each non-scan chain flip-flop which is self-looping with an initializable, non-scan flip-flop;
(b) initializing each flip-flop to a known state;
(c) placing the integrated circuit in a non-operational mode;
(d) shifting a first test vector into the scan chain flip-flops while simultaneously scanning out bits previously shifted into the scan chain flip-flops;
(e) returning the integrated circuit to a normal operating mode;
(f) applying first and second test vectors to the integrated circuit to cause it to generate a response and cause a bit to be shifted into each of the scan chain flip-flops;
(g) compacting the response of the integrated circuit with the bits shifted out of the scan chain flip-flops to yield a stream of bits indicative of the operation of the circuit;
and
(h) repeating steps (c)-(g) a predetermined number of times.

6 more elements

A test system for testing an integrated circuit configured of a plurality of flip-flops, at least one being self-looping and at least a portion of the flip-flops being selected as scan flip-flops and being arranged in a scan chain, to effectuate partial-scan testing of the circuit, comprising:

an initializable flip-flop for replacing each self-looping non-scan flip-flop;
first register means for storing first and second test vectors for input to the chain of scan flip-flops and for input to the integrated circuit, respectively;
controller means coupled to the integrated circuit and to the first register means for:
(a) initializing the integrated circuit;
(b) causing the first and second test vectors from the first test register to be applied to the chain of scan flip-flops and to the integrated circuit, respectively, during a test interval;
and (c) causing the chain of scan flip-flops and the integrated circuit to operate in a non-test (normal) mode following receipt of the first and second test vectors, respectively, so that the integrated circuit generates a response and causes a bit to be shifted into each respective scan chain flip-flop;
and
means coupled to the integrated circuit for compacting the response generated by the integrated circuit with the bits shifted out of the scan chain flip-flops.

5 more elements

Dependencies are inferred from the claim text.

Partial-scan built-in self-test technique

Life of this patent

Partial-scan built-in self-test technique

Life of this patent

Abstract

Claims11