Logic circuit with additional circuit for carrying out delay test

A logic circuit comprising:

• a combination logic for executing at least one predetermined logical function, wherein said combinational logic includes first and second flip-flop circuits connected in series;
• wherein said first and second flip-flop circuits comprise:
• a system data input pin for inputting a system data,
• a first clock input pin for inputting a first clock signal which causes said system data to be stored in a respective one of said first and second flip-flops;
• a scan data input pin for inputting a scan data,
• a second clock input pin for inputting a second clock signal which causes said scan data to be stored in a respective one of said first and second flip-flops,
• first switching means for selecting, in response to a first control signal given to a first control input pin thereof, a destination of a system clock signal for said first flip-flop circuit by switching between said first clock input pin and said second clock input pin of said first flip-flop circuit,
• second switching means for selecting, in response to a second control signal given to a first control input pin thereof, a destination of a system clock signal for said second flip-flop circuit by switching between said first clock input pin and said second clock input pin of said second flip-flop circuit,
• means for generating said first control signal to be given to said first control input pin of said first switching means for effecting said scan data to be input through said scan data input pin of said first flip-flop circuit therein, in response to said system clock signal for said first flip-flop circuit, and
• means for generating said second control signal to be given to said first control input pin of said second switching means for effecting output data of said combination logic to be entered through said system data input pin of said second flip-flop circuit therein, in response to said system clock signal for said second flip-flop circuit.