US 5,329,494 AGranted

Memory cell array divided type semiconductor memory device

AssigneeKabushiki Kaisha Toshiba

InventorsYouichi Suzuki, Takenori Nakamura

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Abstract

The memory device of this invention includes a plurality of memory cell blocks each having a plurality of memory cells disposed in a matrix form. A memory cell selector selects a predetermined number of the memory cells in each memory cell block in accordance with external address signals. A sense amplifier unit amplifies data read from the selected memory cells for data read. A data output unit outputs the data amplified by the sense amplifier unit. A block selector selects a desired one or more of the memory cell blocks as data write blocks for data write. A data write unit writes data in the selected memory cells in the selected blocks. A sense amplifier controller supplies, during the data write, a signal to the sense amplifier unit to make the sense amplifier unit inactive, and during the data read supplies a signal to the sense amplifier unit to make the sense amplifier unit active.

Claims16

Dependent claims

A memory device having any given number of memory blocks, each of the memory blocks, comprising:

a plurality of way cell arrays to and from each of which data can be written and read independently from said other way cell arrays;
memory cell selecting means for selecting a memory cell of each of said way cell arrays on the basis of an external address signal, respectively, the selected memory cells having the same common address mutually in said way cell arrays;
a plurality of sense amplifying means provided for each of said way cell arrays, for sensing and amplifying data read out of the memory cells, said sense amplifying means being allowed to be operative or inoperative in response to a sense control signal in data read/write operations;
data output buffer means for outputting outputs of said sense amplifying means to the outside;
and
a plurality of way write buffer means provided for each of said wall cell arrays, are allowed to be any given number of said way write buffers being selectively operative on the basis of write way control signals, to write data in the selected memory cells of said way cell arrays corresponding thereto.

3 more elements

Dependencies are inferred from the claim text.