Semiconductor memory device having improved connections between word lines and memory cell array blocks

A semiconductor memory device comprising:

• a memory cell array divided into a plurality of blocks respectively having bit lines, word lines, and memory cells coupled to the bit lines and word lines;
• a plurality of sense amplifier means, respectively provided for the blocks and connected to the bit lines, for sensing and amplifying information stored in the memory cells;
• first means, coupled to the word lines of the memory cell array, for selecting one of the word lines for each of the blocks so that at least one of selected word lines is located at a distance from a corresponding one of the plurality of sense amplifier means, said distance being different from distances from other sense amplifier means at which other selected word lines are located;
• and
• second means, coupled to the plurality of sense amplifier means and the first means, for sequentially activating the plurality of sense amplifier means, starting from one of the blocks having one of the selected word lines located at a shortest distance from a corresponding one of the plurality of sense amplifier means.