Two transistor flash EPROM cell
AssigneeAltera Corporation
InventorsAnil Gupta, Kuo-Lung Chen
Life of this patent
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Abstract
A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.
Claims12
A memory cell comprising:
- a word line;
- a write line;
- a read line;
- a first transistor having a gate connected to the word line, a drain to the write line, a source, and a floating gate;
- and
- a second transistor having a gate connected to the word line, a drain connected to the read line, a source and a floating gate connected to the floating gate of the first transistor,
- wherein the floating gate of the second transistor does not extend to either of the source and the drain of the second transistor.
In a flash electrically erasable programmable read only memory having word lines, write lines, read lines, and source lines, and having two-transistor memory cells with a merged transistor having a gate symmetrically aligned with a floating gate, a method of storing data in a selected memory cell comprising contemporaneously:
- applying a first high potential to a write line coupled to the selected cell;
- applying a second high potential to a word line coupled to the selected cell;
- applying first low voltage to a read line coupled to the selected cell;
- and
- applying a second low voltage to a source line coupled to the selected cell.
A nonvolatile memory cell less susceptible to overerasure comprising:
- a first transistor having a gate, a floating gate, a source and a drain;
- a second transistor having a gate connected to the gate of the first transistor, a floating gate connected to the floating gate of the first transistor, a source connected to the source of the first transistor, and a drain;
- and
- wherein the floating gate of the second transistor does not extend to either of the source and the drain.
Dependencies are inferred from the claim text.