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US 5,329,479 AGranted
Dynamic semiconductor memories
AssigneeSharp Kabushiki Kaisha
InventorsYoshiji Ota, Toshio Mimoto
Life of this patent
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Abstract
A dynamic semiconductor memory includes a pair of complementary bit lines with a significant difference in load capacitance, storage capacitors and a pair of transistors for specifying one of the storage capacitors. One end of each storage capacitor is connected to one of the bit lines through one of the transistors and the other end is connected to the other bit line through the other transistor.
Claims2
A dynamic semiconductor memory with memory cell structure comprising
- a first bit line with load capacitance C.sub.1 and a second bit line with load capacitance C.sub.2 for inputting and outputting information, said bit lines being complementary to each other,
- storage capacitor means for storing information, said storage capacitor having capacitance C.sub.S, and
- a first selection means and a second selection means for specifying said storage capacitor means,
- one end of said storage capacitor means being connected to said first bit line through said first selection means and the other end of said storage capacitor means being connected to said second bit line through said second selection means,
- wherein C.sub.1 and C.sub.2 are significantly different from each other, and the voltages of said first and second bit lines depend on C.sub.1, C.sub.2 and C.sub.S.
2 more elements
Dependencies are inferred from the claim text.