Method for optimizing image motion estimation

#1. Field of the Invention

#This invention relates to the field of video processing and, in particular, to the compression and decompression of video signals.

#2. Background Art Statement

#FIG. 1 shows a block diagram representation of a video processing system including a system and method for accelerating the compression and decompression of digital video signals of the present invention.

#FIG. 2 shows a block diagram representation of the pipelined architecture of the system and method for accelerating the compression and decompression of video digital signals of the present invention.

#FIGS. 3A, B show a block diagram representation of the data flow of the system and method of FIG. 2 when it is adapted to encode digital video signals and physical buffer memories for use in this process.

#Referring now to FIG. 1, there is shown remote video processing system 100 including compression/decompression accelerator 120. The bus structure of remote video processing system 100, including address bus 116 and data bus 118, permits easy interconnection of the components of a multimedia display system without using a host processor bus. For example, the local video data of video camera 127 may be received by video processing system 100 by way of line 129 and captured, digitized, subsampled and scaled by video capture 128. The signals provided by video capture 126 may then be processed by system 100 for transmission to merge logic video by way of system output line 132 and capture 128. All of these operations are performed by remote video processing system 100 without use of a host processor bus or an industry standard bus such as bus 140 which may couple remote system 100 to a host computer by way of bus 138. Because system 100 interfaces a source of video data such as video camera 127 to bus 140, system 100 may be understood to be a remote video interface system 100.

#Within video processing system 100 digital video processor 112 performs software processing while accelerator 120 does hardwired functions. Nucleus gate array 121 performs the required memory interface functions. For example, VRAM emulation block 124 makes nucleus gate array 121 function like DRAM with respect to capture 128. Video processing system 100 is therefore limited to the memory configurations supported by nucleus gate array 121.

#In a typical configuration of remote video processing system 100 up to sixteen megabytes of address space may be supported. The first fifteen megabytes of this address space may be reserved for DRAM, for example, DRAM 114, which is interfaced with nucleus gate array 121 by DRAM interface 122. The upper one megabyte of the memory space of video processing system 100 is reserved for communication between various devices which may be coupled to address bus 116 and data bus 118. Compression/decompression accelerator 120 may occupy the first one hundred twenty-eight kilobytes of the communication area in the upper one megabyte of memory space.