Synthetic aperture radar digital signal processor

In a digital signal processor of the type having two channels, each with a multiplier/accumulator fed by first and second data inputs and a first reference input, the improvement comprising:

• a second reference input;
• a pair of multipliers following the multiplier/accumulators, each multiplier being associated with a channel, one input to the multiplier associated with the first channel being the output of the first-channel multiplier/accumulator, one input to the multiplier associated with the second channel being the output of the second-channel multiplier/accumulator, and the other input to each multiplier being the second reference input;
• and
• a pair of adders following the second multipliers, each adder being associated with a channel, one input to the adder associated with the first channel being the output of the first-channel multiplier, one input to the adder associated with the second channel being the output of the second-channel multiplier, the other adder inputs being said data inputs.

A digital signal processor optimized for synthetic aperture radar image formation adapted for use in conjunction with a memory device, the processor comprising:

• a first data-input port;
• a second data-input port;
• data-select logic connected to said first and said second data input ports, said logic being operative to output the data from either port to any of a first-stage I channel, a first-stage Q channel, a second-stage I channel or a second-stage Q channel;
• a first-stage reference input port;
• reference-path logic having a first input to receive data from said first-stage reference input port, a second input to receive data from said first-stage I channel, and a third input adapted to receive data from said first-stage Q channel, said reference-path logic being operative to route any one of said inputs to either a first output or a second output;
• swapping logic having a first input to receive data from said first-stage I channel and a second input to receive data from said first-stage Q channel, said swapping logic being operative to output either of said inputs to either a first output or a second output;
• a first multiplier stage having a first multiplier/accumulator and a second multiplier/accumulator, each with two inputs, the inputs to the first multiplier/accumulator being the first output of said swapping logic and the first output of said reference-path logic, the inputs to the second multiplier/accumulator being the second output of said swapping logic and the second output of said reference-path logic;
• a second-stage reference input port;
• a second multiplier stage having a first multiplier and a second multiplier, each with two inputs, one input to the first multiplier being the output of the first multiplier/accumulator, one input to the second multiplier being the output of the second multiplier/accumulator, and the other input to each multiplier being connected to said second-stage reference input port;
• and
• a first negate/pass circuit connected to the output of the first multiplier, and a second negate/pass circuit connected to the output of the second multiplier, each negate/pass circuit being operative to produce an output by either negating its input or by passing its input through unchanged;
• a first adder and a second adder, each with two inputs, one input to the first adder being the output of the first negate/pass circuit, the other input to the first adder being the second-stage I-channel, one input to the second adder being the output of the second negate/pass circuit, the other input to the second adder being the second-stage Q-channel;
• an output scaler connected to the outputs of the adders, the output scaler being operative to numerically scale its inputs and provide an output to an output data port;
• a plurality of digital differential analyzers configured as data and reference address generators, the generators being operative to provide addresses to said memory device, the contents of the memory thus retrieved being used as said data and reference inputs;
• an I/O controller operative to manage data, address and control signals required by, and generated by, said processor in conjunction with external devices;
• and
• a user-programmable control sequencer connected to the data-select logic, reference path logic, swapping logic, multiplier/accumulators, multipliers, negate/pass circuits, adders, output scaler, digital differential analyzers, I/O controller and memory device , the sequencer being operative to coordinate and control the overall functioning of said processor and cause said address generators to generate data and reference addresses.