Modular video subsystem partitioning interface

An interface for a video screen control card that connects at least one type of video screen to a computer system, wherein the interface between the control card and system comprises;

• at least one pin that provides access to a signal generated by the control card, which indicates to the system that the control card accepts memory in 16 bits;
• at least one pin that provides access to a signal generated by the control card, which indicates to the system that the card accepts I/O in 16 bits;
• at least one pin that provides access to a high byte enable signal generated by the system;
• at least one pin that provides access to a direct memory access enable signal generated by the system;
• at least one pin that provides access to an I/O ready signal generated by the control card;
• at least one pin that provides access to a monitor interrupt request signal generated by the control card;
• at least one pin that provides access to a system reset signal generated by the system;
• at least one pin that provides access to an I/O write strobe signal generated by the system;
• at least one pin that provides access to an I/O read strobe signal generated by the system;
• at least one pin that provides access to a memory read strobe signal generated by the system;
• at least one pin that provides access to a memory write strobe signal generated by the system;
• at least one pin that provides access to a memory refresh signal generated by the system;
• at least one pin that provides access to a first low power control signal generated by the system;
• at least one pin that provides access to a system clock signal generated by the system;
• at least one pin that provides access to a high byte data bus;
• at least one pin that provides access to a low byte data bus;
• at least one pin that provides access to at least one unlatched address bit signal generated by the system;
• at least one pin that provides access to at least one latched address bit signal generated by the system;
• at least one pin that provides access to a clock signal generated by the system for said unlatched address bit;
• at least one pin that provides access to an active display signal generated by the control card that indicates which screen type is operatively connected to the system;
• at least one pin that provides access to a signal generated by the system that request memory addresses in the control card memory;
• at least one pin that provides access to a second low power control signal generated by the system;
• at least one pin that provides access to a monitor control powerdown signal generated by the system;
• at least one pin that provides access to a power supply from the system having a first predetermined voltage;
• at least one pin that provides access to a power supply from the system having a second predetermined voltage;
• at least one pin that provides access to a power supply from the system having a third predetermined voltage;
• at least one pin that provides access to a power supply from the system having a fourth predetermined voltage;
• at least one pin that provides access to ground;
• at least one pin that provides access to a LCD data strobe signal generated by the system;
• and,
• at least one pin that provides access to a LCD data bus.

An interface for a control card connected to a computer system, wherein the control card has an output port for a video monitor screen and an output port for a LCD screen, wherein the interface between the control card and system comprises;

• at least one pin that provides access to a signal generated by the control card, which indicates to the system that the control card accepts memory in 16 bits;
• at least one pin that provides access to a signal generated by the control card, which indicates to the system that the card accepts I/O in 16 bits;
• at least one pin that provides access to a high byte enable signal generated by the system;
• at least one pin that provides access to a direct memory access enable signal generated by the system;
• at least one pin that provides access to a monitor interrupt request signal generated by the control card;
• at least one pin that provides access to a system reset signal generated by the system;
• at least one pin that provides access to an I/O write strobe signal generated by the system;
• at least one pin that provides access to an I/O read strobe signal generated by the system;
• at least one pin that provides access to a memory read strobe signal generated by the system;
• at least one pin that provides access to a memory write strobe signal generated by the system;
• at least one pin that provides access to a first low power control signal generated by the system;
• at least one pin that provides access to a memory refresh signal generated by the system;
• at least one pin that provides access to a system clock signal generated by the system;
• at least one pin that provides access to a high byte data bus;
• at least one pin that provides access to a low byte data bus;
• at least one pin that provides access to at least one unlatched address bit signal generated by the system;
• at least one pin that provides access to at least one latched address bit signal generated by the system;
• at least one pin that provides access to a clock signal generated by the system for said unlatched address bit;
• at least one pin that provides access to an active display signal generated by the control card that indicates which screen type is operatively connected to the system;
• at least one pin that provides access to a signal generated by the system that request memory addresses in the control card memory;
• at least one pin that provides access to a second low power control signal generated by the system;
• at least one pin that provides access to a monitor control powerdown signal generated by the system;
• at least one pin that provides access to a power supply from the system having a first predetermined voltage;
• at least one pin that provides access to a power supply from the system having a second predetermined voltage;
• at least one pin that provides access to a power supply from the system having a third predetermined voltage;
• at least one pin that provides access to a power supply from the system having a fourth predetermined voltage;
• at least one pin that provides access to ground;
• at least one pin that provides access to a LCD data strobe signal generated by the system;
• and,
• at least one pin that provides access to a LCD data bus.

An interface for a video screen control card that connects at least one type of video screen to a computer system, wherein the interface between the control card and system comprises;

• pin 1 which provides access to a signal generated by the control card which indicates to the system that the control card will accept memory in 16 bits;
• pin 2 which provides access to a clock signal generated by the system for unlatched address bit signals;
• pin 3 which provides access to a high byte enable signal generated by the system;
• pin 4 which provides access to a direct memory access enable signal generated by the system;
• pin 5 which provides access to a monitor interrupt request signal generated by the control card;
• pin 6 which provides access to an I/O ready signal generated by the control card;
• pin 7 which provides access to a system reset signal generated by the system;
• pin 8 which provides access to an I/O write strobe signal generated by the system;
• pin 9 which provides access to an I/O read strobe signal generated by the system;
• pin 10 which provides access to a memory read strobe signal generated by the system;
• pin 11 which provides access to a memory write strobe signal generated by the system;
• pin 12 which provides access to a memory refresh signal generated by the system;
• pin 13 which provides access to a second low power control signal;
• pin 14 which provides access to a signal generated by the control card which indicates to the system that the control card will accept I/O in 16 bits;
• pin 15 which provides access to ground;
• pin 16 which provides access to a system clock signal generated by the system;
• pins 17-18 which provide access to ground;
• pins 19-26 which provide access to a high byte data bus between the system and the control card;
• pin 27 which provides access to ground;
• pins 28-29 which provide access to a +5 volt power supply from the system;
• pin 30 which provides access to ground;
• pins 31-38 which provide access to a low byte data bus;
• pin 39 which provides access to a +5 volt power supply from the system;
• pin 40 which provides access to ground;
• pins 41-43 which provide access to 3 unlatched address bit signals generated by the system;
• pins 44-50 which provide access to 7 latched address bit signals from the system;
• pins 51-52 which provide access to a +5 volt power supply from the system;
• pin 53 which provides access to ground;
• pins 54-63 which provide access to 10 latched address bit signals generated by the system;
• pin 64 which provides access to ground;
• pin 65 which provides access to an active display signal generated by the control card that indicates which screen type is operatively connected to the system;
• pin 66 which provides access to a signal generated by the system that request memory addresses in the control card memory;
• pin 67 which provides access to a first low power control signal generated by the system;
• pin 68 which provides access to a -24 volt power supply from the system;
• pin 69 which provides access to a +12 volt power supply from the system;
• pin 70 which provides access to a +14.4 volt power supply from the system;
• pin 71 which provides access to a monitor control powerdown signal generated by the system;
• pin 72 which provides access to a LCD data strobe generated by the system;
• pin 73 which provides access to a LCD data bus between the system and control card;
• and,
• pins 74-80 which provide access to ground.

An interface for a control card connected to a computer system, wherein the control card has an output port for a video monitor screen and an output port for a LCD screen, wherein the interface between the control card and system comprises;

• pin 1 which provides access to a signal generated by the control card which indicates to the system that the control card will accept memory in 16 bits;
• pin 2 which provides access to a clock signal generated by the system for unlatched address bit signals;
• pin 3 which provides access to a high byte enable signal generated by the system;
• pin 4 which provides access to a direct memory access enable signal generated by the system;
• pin 5 which provides access to a monitor interrupt request signal generated by the control card;
• pin 6 which provides access to an I/O ready signal generated by the control card;
• pin 7 which provides access to a system reset signal generated by the system;
• pin 8 which provides access to an I/O write strobe signal generated by the system;
• pin 9 which provides access to an I/O read strobe signal generated by the system;
• pin 10 which provides access to a memory read strobe signal generated by the system;
• pin 11 which provides access to a memory write strobe signal generated by the system;
• pin 12 which provides access to a memory refresh signal generated by the system;
• pin 13 which provides access to a second low power control signal;
• pin 14 which provides access to a signal generated by the control card which indicates to the system that the control card will accept I/O in 16 bits;
• pin 15 which provides access to ground;
• pin 16 which provides access to a system clock signal generated by the system;
• pins 17-18 which provide access to ground;
• pins 19-26 which provide access to a high byte data bus between the system and the control card;
• pin 27 which provides access to ground;
• pins 28-29 which provide access to a +5 volt power supply from the system;
• pin 30 which provides access to ground;
• pins 31-38 which provide access to a low byte data bus;
• pin 39 which provides access to a +5 volt power supply from the system;
• pin 40 which provides access to ground;
• pins 41-43 which provide access to 3 unlatched address bit signals generated by the system;
• pins 44-50 which provide access to 7 latched address bit signals from the system;
• pins 51-52 which provide access to a +5 volt power supply from the system;
• pin 53 which provides access to ground;
• pins 54-63 which provide access to 10 latched address bit signals generated by the system;
• pin 64 which provides access to ground;
• pin 65 which provides access to an active display signal generated by the control card that indicates which screen type is operatively connected to the system;
• pin 66 which provides access to a signal generated by the system that request memory addresses in the control card memory;
• pin 67 which provides access to a first low power control signal generated by the system;
• pin 68 which provides access to a -24 volt power supply from the system;
• pin 69 which provides access to a +12 volt power supply from the system;
• pin 70 which provides access to a +14.4 volt power supply from the system;
• pin 71 which provides access to a monitor control powerdown signal generated by the system;
• pin 72 which provides access to a LCD data strobe generated by the system;
• pin 73 which provides access to a LCD data bus between the system and control card;
• and,
• pins 74-80 which provide access to ground.