Semiconductor integrated circuit having clock signal generator

A semiconductor integrated circuit having a clock signal generator comprising:

• a ring oscillator having a plurality of selectively operable switches connected in series and a plurality of delay units connected with said switches for providing variable oscillating frequencies determined by a sum of the delay times provided by said delay units;
• a divider for dividing the oscillation frequency given from said ring oscillator by a specified number;
• a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of an external clock signal given from the outside;
• an up-down counter for controlling the oscillation frequency of said ring oscillator by operating said switches, based on the comparison result from said phase comparator;
• and
• means for operating said switches in response to operation of said up-down counter;
• wherein said clock signal generator, controlled by said externally entered clock signal to generate an internal clock signal of which frequency is higher than the frequency of said externally entered clock signal, outputs both internal and external clock signals.

A semiconductor integrated circuit having a clock signal generator comprising:

• a ring oscillator having a plurality of selectively operable switches connected in series and a plurality of delay units connected with said switches for providing variable oscillating frequencies determined by a sum of the delay times provided by said delay units;
• a divider for dividing the oscillation frequency given from said ring oscillator by a specified number;
• a phase comparator for comparing the frequency of the output signal given from said divider with the frequency of an external clock signal given from the outside;
• an up-down counter for controlling the oscillation frequency of said ring oscillator by operating said switches, based on the comparison result from said phase comparator;
• and
• means for operating said switches in response to operation of said up-down counter;
• wherein said clock signal generator generates an internal clock signal having a frequency which is higher than the frequency of said externally entered clock signal to operate the circuit elements internal to said clock signal generator at a high speed.