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US 5,329,253 AGranted
Frequency synthesis using frequency controlled carrier modulated with PLL feedback signal
AssigneeNEC Corporation
InventorMasaki Ichihara
Life of this patent
Estimating the term…
Abstract
In a frequency synthesizer, a phase detector receives an externally generated reference clock signal of a constant frequency and a feedback signal to produce an error signal, which is output through a loop filter to a voltage controlled oscillator. A direct digital synthesizer (DDS) receives the reference clock signal and externally generated phase data to produce a DDS output signal whose frequency is precisely controlled by the phase data. The DDS output signal is applied as a carrier to a differential detector where it is modulated with the output of the VCO to produce a signal corresponding to the lower sideband of the modulated carrier. The output of the differential detector is output to the phase detector as the feedback signal.
Claims10
A frequency synthesizer comprising:
- a divide-by-M frequency divider for receiving an externally generated reference clock signal of constant frequency and producing a frequency-divided reference clock signal;
- a phase detector having a reference input for receiving said frequency-divided reference clock signal, a feedback input, and a phase detector output;
- a loop filter having an input coupled to said phase detector output, and a loop filter output;
- a voltage controlled oscillator having an input coupled to said loop filter output, and an oscillator output for providing a synthesizer output signal;
- a divide-by-N frequency divider connected to said oscillator output for producing a frequency-divided synthesizer output signal;
- a direct digital synthesizer (DDS) having a clock input for receiving said externally generated reference clock signal, a frequency control input for receiving externally generated phase data, and a DDS output;
- and
- differential detector means having a first input for receiving the frequency-divided synthesizer output signal from the divide-by-N frequency divider, a second input coupled to said DDS output for producing a differential signal indicative of a frequency difference between signals at said first and second inputs, and a differential detector output coupled to the feedback input of the phase detector for providing the differential signal thereto.
5 more elements
A frequency synthesizer comprising:
- reference clock means for generating a reference clock signal;
- first divider means for receiving the reference clock signal and dividing the frequency of the reference clock signal by M and producing a frequency-divided reference clock signal;
- phase detector means for receiving said frequency-divided reference clock signal and a feedback signal, detecting a phase differential between said frequency-divided reference clock signal and said feedback signal and producing a corresponding error signal;
- loop filter means for filtering noise in said error signal and producing a filtered error signal;
- variable oscillator means for generating a variable oscillator output signal in response to said filtered error signal;
- second divider means for receiving the variable oscillator output signal, dividing the frequency of the variable oscillator output signal by N and producing a frequency-divided variable oscillator output signal;
- phase accumulator means for receiving a digital frequency control signal indicative of a phase increment value and accumulating phase increment values at a rate corresponding to said reference clock signal from said reference clock means, and producing an accumulator output signal corresponding to the accumulated phase increment values;
- memory means for storing a plurality of digital amplitude values representing instantaneous amplitude values of an analog periodic signal and producing a memory output signal indicative of the digital amplitude value corresponding to each accumulated phase increment value of said accumulator output signal;
- converter means for converting the digital amplitude values of the memory output signal to analog amplitude values, and producing a corresponding analog periodic signal;
- and
- mixer means for modulating said periodic signal from said converter means with said frequency-divided variable oscillator output signal, producing a mixer output signal indicative of the modulated periodic signal, and providing the mixer output signal to said phase detector means as said feedback signal.
8 more elements
A frequency synthesizer comprising:
- reference clock means for generating a reference clock signal;
- phase detector means for receiving said reference clock signal and a feedback signal, detecting a phase difference between said reference clock signal and said feedback signal and producing a corresponding error signal;
- loop filter means for filtering noise in said error signal and producing a filtered error signal;
- variable oscillator means for generating a variable oscillator output signal in response to said filtered error signal;
- first phase accumulator means for receiving a digital frequency control signal indicative of a first phase increment value and accumulating first phase increment values at a rate corresponding to said reference clock signal, and producing a first accumulator output signal corresponding to the accumulated first phase increment values;
- second phase accumulator means for receiving a digital signal of a constant value indicative of a second phase increment value and accumulating second phase increment values at a rate corresponding to said variable oscillator output signal, and producing a second accumulator output signal corresponding to the accumulated second phase increment values;
- subtractor means for receiving said first and second accumulator output signals, detecting accumulated phase difference values between the accumulated first phase increment values and the accumulated second phase increment values, and producing a corresponding subtractor output signal;
- memory means for storing a plurality of digital amplitude values representing instantaneous amplitude values of an analog periodic signal and producing a memory output signal indicative of the digital amplitude value corresponding to each accumulated phase difference value of said subtractor output signal;
- and
- converter means for converting the digital amplitude values of the memory output signal to analog amplitude values, producing a corresponding analog period signal, and providing the analog periodic signal as said feedback signal.
7 more elements
Dependencies are inferred from the claim text.