Multiple biasing phase-lock-loops controlling center frequency of phase-lock-loop clock recovery circuit

A method for generating a recovered clock signal having a plurality of selectable center frequencies that are phase aligned with timing data that has been extracted by a digital signal processor from an input data signal, the method comprising the steps of:

• generating a first biasing signal having a magnitude that is a function of the frequency of a first clock signal;
• generating a second biasing signal having a magnitude that is a function of the frequency of a second clock signal;
• selecting either the first biasing signal or the second biasing signal as a selected bias signal in response to a select signal;
• generating the recovered clock signal in response to a phase error signal, the center frequency of the recovered clock signal being a function of the magnitude of the phase error signal;
• and
• generating the phase error signal by modifying the selected bias signal with a digital error word generated by the digital signal processor, the digital error word representing a phase difference between the recovered clock signal and the timing data;
• whereby the center frequency of the recovered clock signal is principally determined by the selected bias signal, and
• whereby the phase of the recovered clock signal is adjusted so as to reduce any phase difference between the recovered clock signal and the timing data.

A recovered clock circuit for generating a recovered clock signal having a plurality of selectable center frequencies, the recovered clock circuit being connectable with a digital signal processor (DSP) to form a phase-lock-loop (PLL), the DSP generating a digital error word in response to a phase difference between the recovered clock signal and timing data extracted by the DSP from an input data signal, the recovered clock circuit comprising:

• a first biasing PLL that generates a first biasing signal having a magnitude that is a function of the frequency of a first clock signal;
• a second biasing PLL that generates a second biasing signal having a magnitude that is a function of the second frequency of a second clock signal;
• a multiplexor that passes either the first biasing signal or the second biasing signal as a selected bias signal in response to a select signal;
• a primary controlled oscillator that generates the recovered clock signal in response to a DSP generated restart signal and a phase error signal, the center frequency of the recovered clock signal being a function of the magnitude of the phase error signal;
• and
• a digital-to-analog converter that generates the phase error signal by modifying the selected bias signal with the digital error word;
• whereby the center frequency of the recovered clock signal is principally determined by the selected bias signal, and
• whereby the phase of the recovered clock signal is adjusted so as to reduce any phase difference between the recovered clock signal and the timing data.