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US 5,329,240 AGranted
Apparatus for measuring clock pulse delay in one or more circuits
AssigneeFujitsu Limited
InventorsKatsuhisa Kubota, Kunitoshi Yamamoto, Kazuharu Nakano
Life of this patent
Estimating the term…
Abstract
A clock adjustment system for economically adjusting the output phases of a printed circuit board and an IC comprises a gate circuit for connecting an input of a measured circuit to an output. By turning the gate circuit on and by observing the oscillation of a measured circuit, the phase of the measured circuit is adjusted.
Claims8
A clock adjustment circuit for measuring a delay of a measured circuit comprising:
- a pulse forming circuit for generating a clock pulse,
- a phase adjusting circuit supplied with said clock pulse at its input terminal, said phase adjusting circuit distributing said supplied clock pulse to a plurality of LSIs in a measured circuit and adjusting the phases of respective LSI clock pulses which are distributed to said LSIs;
- a selected one of said LSIs operating in response to said distributed clock pulse supplied from said phase adjusting circuit, said LSI executing an operation by providing an output signal responsive to said distributed clock pulse;
- trigger means for outputting a signal as a trigger out of a rise edge or a fall edge of a signal received from said selected LSI depending on whether or not an inverse logic of said clock pulse is generated when said LSI operation is executed;
- feedback means for receiving said output signal from said trigger means, and supplying said output signal to an input terminal of said pulse forming circuit;
- and
- means for measuring the delay of said measured circuit receiving said distributed clock pulse by measuring an oscillation generated by said clock pulse generated by said pulse forming circuit, and said output signal of said trigger means.
4 more elements
A clock adjustment circuit comprising:
- a pulse forming circuit;
- an output of said pulse forming circuit being connected to an input of a measured circuit, and an input of said pulse forming circuit being connected to an output of said measured circuit;
- said pulse forming circuit comprising:
- a gate circuit having an input which receives an output from said measured circuit;
- and
- a pulse generation circuit for receiving an output from said gate circuit at a first input of said pulse generation circuit, said pulse generation circuit generating a pulse of a predetermined width at a rise or a fall of a trigger signal received at a second input of said pulse generation circuit;
- said pulse generation circuit further comprising:
- a first differential circuit for differentiating said trigger signal, said trigger signal being supplied to an input of said first differential circuit;
- a set-reset flip-flop set at least by an output from either said gate circuit or said first differential circuit, said output of said set-reset flip-flop being the output from said pulse generating circuit;
- a first delay means responsive to said set-reset flip-flop output for generating an output which is delayed by a predetermined time from said set-reset flip-flop output;
- and
- a second differential circuit responsive to said output of said first delay means for differentiating an output from said first delay means and for resetting said set-reset flip-flop;
- said pulse forming circuit further comprising a frequency counter responsive to said output of said measured circuit for measuring a delay in said measured circuit from a repetition cycle of an oscillation generated when said gate circuit is turned on.
10 more elements
Dependencies are inferred from the claim text.