High speed differential comparator

A differential comparator comprising:

• first and second input terminals for the application thereto of first (V1) and second (V2) input signals to be compared;
• first and second capacitors, each capacitor having a first and a second plate;
• a selectively enabled first switch means connected between said first input terminal and the first plate of said first capacitor;
• a selectively enabled second switch means connected between said second input terminal and the first plate of said second capacitor;
• a first amplifier with a first input, a first output, and a first autozeroing subcircuit coupling said first output to said first input when said first subcircuit is active;
• a second amplifier with a second input, a second output, and a second autozeroing subcircuit coupling said second output to said second input when said second subcircuit is active;
• means direct current connecting the first input of said first amplifier to the second plate of said first capacitor;
• means direct current connecting the second input of said second amplifier to the second plate of said second capacitor;
• and
• first and second feedback connectors, said first feedback connector being directly and permanently connected between said first output and said second input, and said second feedback connector being directly and permanently connected between said second output and said first input;
• whereby a differential signal at said first and second inputs is latched by said amplifiers when said first and second subcircuits change from active to inactive.

A differential comparator comprising:

• first and second input terminals for the application thereto of first (V1) and second (V2) input signals to be compared;
• first and second capacitors, each capacitor having a first and a second plate;
• a selectively enabled first switch means connected between said first input terminal and the first plate of said first capacitor;
• a selectively enabled second switch means connected between said second input terminal and the first plate of said second capacitor;
• a first amplifier with a first input, a first output, and a first autozeroing subcircuit coupling said first output to said first input when said first subcircuit is active;
• a second amplifier with a second input, a second output, and a second autozeroing subcircuit coupling said second output to said second input when said second subcircuit is active;
• means direct current connecting the first input of said first amplifier to the second plate of said first capacitor;
• means direct current connecting the second input of said second amplifier to the second plate of said second capacitor;
• and
• first and second passive feedback networks, said first feedback network coupling said first output to said second input, and said second feedback network coupling said second output to said first input;
• whereby a differential signal at said first and second inputs is latched by said amplifiers when said first and second subcircuits change from active to inactive;
• a selectively enabled third switch means connected between the first plate of the first capacitor and the first plate of the second capacitor;
• and
• means coupled to said first, second, and third selectively enabled switch means for enabling said first and second switch means and disabling said third switch means during a first time internal;
• and for disabling said first and second switch means and enabling said third switch during a second time interval,
• said third switch means when enabled for combining said first signal (V1) at said first plate of said first capacitor and said second signal (V2) at said first plate of said second capacitor and producing a combined voltage (Vc) at the first plate of said first and second capacitor which has a value between V1 and V2, when V1 and V2 have different values, and for producing a voltage (Vc-V1) at the second plate of the first capacitor and a voltage (Vc-V2) at the second plate of the second capacitor, thereby producing A.C. signals of opposite polarity at the second plates of the first and second capacitors.

A combination comprising:

• first and second capacitors each having first and second plates;
• first switch means for selectively applying a first signal (V1) to the first plate of the first capacitor during a first time interval;
• second switch means for selectively applying a second signal (V2) to the first plate of the second capacitor during said first time interval;
• means for placing a first D.C. voltage level on the second plate of the first capacitor and a second D.C. voltage level on the second plate of the second capacitor;
• and
• third switch means for selectively shorting the first plates of the first and second capacitors together during a second time interval, subsequent to said first time interval, for combining V1 and V2 and producing a combined voltage (Vc) at the first plate of said first and second capacitor which has a value between V1 and V2, when V1 and V2 have different values, and for producing a voltage (Vc-V1) at the second plate of the first capacitor and a voltage (Vc-V2) at the second plate of the second capacitor, thereby producing A.C. signals of opposite polarity at the second plates of the first and second capacitors.