CMOS logic circuitry providing improved operating speed
AssigneeGTE Laboratories Incorporated
InventorsMichael Cooperman, Phillip Andrade
Life of this patent
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Abstract
Electrical circuitry of CMOS inverter circuits in cascade providing a compatible interface between ECL logic levels and CMOS logic levels. The MOS transistors of the first inverter circuit of the series are approximately three times larger than the MOS transistors of the same type in subsequent inverter circuits of the series. The ECL input is to the gate of the N-type transistor of the first inverter circuit. A threshold control input is connected to the gate of the P-type transistor of the first inverter circuit. This configuration increases the operating speed of the first inverter circuit and permits controlling the threshold voltage in order to stabilize the output duty cycle.
Claims5
Electrical circuitry providing a compatible interface between emitter coupled logic levels and CMOS logic levels including:
- first and second inverter circuits, each inverter circuit comprising a complementary pair of MOS transistors connected in series between a first voltage source and a second voltage source to provide compatibility between emitter coupled logic and CMOS logic levels;
- an input connection connected to the gate on one of the MOS transistors of the first inverter for receiving input signals of the range of emitter coupled logic signals;
- a control connection connected to the gate of the other of the MOS transistors of the first inverter circuit;
- the juncture of the MOS transistors of the first inverter circuit being connected to the gates of the MOS transistors of the second inverter circuit;
- and
- said MOS transistors of the first inverter circuit being larger than the MOS transistors of the same type of the second inverter circuit thereby providing greater drive capability to compensate for the relatively small range of emitter coupled logic input signals applied to the first inverter circuit.
Dependencies are inferred from the claim text.