US 5,329,182 AGranted

ATD pulse generator circuit with ECL to CMOS level conversion

AssigneeMotorola, Inc.

InventorRuey J. Yu

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Abstract

An ATD pulse generator circuit (20) provides an ATD pulse at CMOS logic levels in response to a single-ended ECL level input signal transition. An emitter-follower input portion (21), a differential amplifier (23), and emitter-follower portion (25) converts the single-ended input signal to intermediate level differential signals. P-channel transistors (51 and 52) receive the intermediate level differential signals and provide complementary CMOS level outputs signals. Cross-coupled delay portion (29) prevents the N-channel transistors (55 and 56) from switching on until after a delay, causing both of the CMOS level output signals to remain at logic high levels for a predetermined time. Cross-coupling the N-channel transistors (55 and 56) also results in reduced power consumption. A NAND gate (31) receives the logic high levels and provides a CMOS level ATD pulse, the duration of which is adjustable.

Claims18

Dependent claims

A circuit for receiving an ECL level input signal and for

providing a CMOS level output pulse, comprising:
input means for receiving the ECL level signal, and in response, providing first and second complementary signals;
a first MOS transistor having a first current electrode for receiving said first complementary signal, a control electrode for receiving a reference voltage, and a second current electrode for providing a first CMOS level output signal;
a second MOS transistor having a first current electrode for receiving said second complementary signal, a control electrode for receiving said reference voltage, and a second current electrode for providing a second CMOS level output signal;
first delay means having a first terminal coupled to said second current electrode of said first MOS transistor, and a second terminal;
second delay means having a first terminal coupled to said second current electrode of said second MOS transistor, and a second terminal;
first current source means, coupled to said second current electrode of said first MOS transistor and to said second terminal of said second delay means, for providing a current for said first MOS transistor a predetermined time after said second CMOS level output signal is received;
second current source means, coupled to said second current electrode of said second MOS transistor and to said second terminal of said first delay means, for providing a current for said second MOS transistor said predetermined time after said first CMOS level output signal is received;
and
logic means for providing a CMOS level output pulse in response to receiving said first and second CMOS level output signals, a duration of said output pulse being determined by said predetermined time.

7 more elements

An address transition detection pulse generator circuit, comprising:

input means for receiving an ECL level address signal, and in response, providing first and second complementary signals of a predetermined logic level;
a first P-channel transistor having a first current electrode for receiving said first complementary signal, a gate for receiving a reference voltage, and a second current electrode for providing a first CMOS level output signal;
a second P-channel transistor having a first current electrode for receiving said second complementary signal, a gate for receiving said reference voltage, and a second current electrode for providing a second CMOS level output signal;
first delay means for receiving said first CMOS level output signal, and in response, providing a first delayed signal after a predetermined delay;
second delay means for receiving said second CMOS level output signal, and in response, providing a second delayed signal after said predetermined delay;
a first N-channel transistor having a drain connected to the second current electrode of said first P-channel transistor, a gate for receiving said second delayed signal, and a source coupled to a negative power supply voltage terminal;
a second N-channel transistor having a drain connected to the second current electrode of said second P-channel transistor, a gate for receiving said first delayed signal, and a source coupled to said negative power supply voltage terminal;
and
logic means for receiving said first and second CMOS level output signals, and in response, providing a CMOS level address transition detection pulse.

6 more elements

An integrated circuit memory, comprising:

an array of memory cells, each memory cell of the array of memory cells providing a pair of complementary data signals when selected;
address means, coupled to said array of memory cells, for receiving an ECL level external address signal, and in response, selecting a memory cell;
input means for receiving said ECL level external address signal, and in response, providing first and second complementary signals of a predetermined logic level;
a first MOS transistor having a first current electrode for receiving said first complementary signal, a control electrode for receiving a reference voltage, and a second current electrode for providing a first CMOS level output signal;
a second MOS transistor having a first current electrode for receiving said second complementary signal, a control electrode for receiving said reference voltage, and a second current electrode for providing a second CMOS level output signal;
first delay means having a first terminal coupled to said second current electrode of said first MOS transistor, and a second terminal;
second delay means having a first terminal coupled to said second current electrode of said second MOS transistor, and a second terminal;
first current source means, coupled to said second current electrode of said first MOS transistor and to said second terminal of said second delay means, for providing a current for said first MOS transistor a predetermined time after said second CMOS level output signal is received;
second current source means, coupled to said second current electrode of said second MOS transistor and to said second terminal of said first delay means, for providing a current for said second MOS transistor said predetermined time after said first CMOS level output signal is received;
and
logic means for receiving said first and second CMOS level output signals, and in response, providing a CMOS level output pulse.

8 more elements

Dependencies are inferred from the claim text.