Self-timed clocking system and method for self-timed dynamic logic circuits

A method for utilizing a self-timed dynamic logic block having precharge and evaluation periods at a rate which is faster than a system clock while maintaining synchronous operation with the system clock, comprising the steps of:

• (1) providing a triggering signal which is synchronous to the system clock;
• and
• (2) performing the following steps during a period of the system clock;
• (a) performing a first self-timed logic evaluation on a first vector input at the rising edge of said triggering signal;
• (b) generating a first precharge upon detecting the vector output as valid;
• (c) performing a second self-timed logic evaluation on a second vector input at the falling edge of said triggering signal;
• and
• (d) generating a second precharge upon detecting the second vector output as valid.

A system for enhancing the speed of logic evaluations through a self-timed dynamic logic block having precharge and evaluation periods, the system comprising:

• a logic block having inputs and an output, said logic block having cascaded dynamic logic gates which are precharged during the precharge period and which performs a self-timed logic evaluation on said inputs to derive said output during the evaluation period;
• an evaluation done detector connected to said output, said evaluation done detector for determining when said logic block has completed said logic evaluation by sensing said output and for causing termination of said evaluation period;
• and
• means connected to said logic block and to said evaluation done detector, said means for receiving a periodic timing signal, said means for terminating said evaluation period and for commencing said precharge period by applying a precharge to said logic block after said logic block has completed said logic evaluation, said means for terminating said precharge period by terminating application of said precharge and for commencing said evaluation period at each change of logic state of said periodic timing signal.

A system for utilizing a self-timed dynamic logic block having precharge and evaluation periods at a rate which is twice as fast as a system clock while maintaining synchronous operation with the system clock, the system comprising:

• a logic block having inputs and an output, said logic block having cascaded dynamic logic gates which are precharged during the precharge period and which performs a self-timed logic evaluation on said inputs to derive said output during the evaluation period;
• an evaluation done detector connected to said output, said evaluation done detector for determining when said logic block has completed said logic evaluation by sensing said output and for causing termination of said evaluation period;
• and
• means connected to said logic block and to said evaluation done detector, said means for receiving the system block, said means for terminating said evaluation period and for connecting said precharge period by applying a precharge to said logic block after said logic block has completed said logic evaluation, said means for terminating said precharge period by terminating application of said precharge and for commencing said evaluation period at each change of logic state of said system clock.

A method for enhancing the speed of logic evaluations through a self-timed dynamic logic block having inputs and an output and having precharge and evaluation periods, the method comprising the steps of:

• receiving a periodic timing signal;
• terminating said precharge period and commencing said evaluation period at each change of logic state of said periodic timing signal;
• performing a self-timed logic evaluation on the inputs to derive the output during said evaluation period;
• detecting when said evaluation is complete by monitoring the output;
• and
• terminating said evaluation period and connecting application of a precharge to the logic block after detecting completion of said logic evaluation.

A method for utilizing self-timed dynamic logic block having precharge and evaluation periods at a rate which is twice the speed of a system clock while maintaining synchronous operation with the system clock, the method comprising the steps of:

• receiving the system clock;
• terminating said precharge period and commencing said evaluation period at each change of logic state of said system clock;
• performing a self-timed logic evaluation on the inputs to derive the output during said evaluation period;
• detecting when said evaluation is complete by monitoring the output;
• and
• terminating said evaluation period and commencing application of a precharge to the logic block after detecting completion of said logic evaluation.