Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
AssigneeLSI Logic Corporation
InventorMichael D. Rosotker
Life of this patent
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AssigneeLSI Logic Corporation
InventorMichael D. Rosotker
Estimating the term…
A greater lead count for a given die area can be achieved with "certain non-square" geometries formed by the inner ends of conductive lines. These include various triangular configurations, as well as "greatly elongated" rectangular, parallelogram and trapezoidal configurations. The conductive lines may be leads of a lead frame, leads on a tape-based package, or traces on ceramic or PCB-substrate packages. The package body may be formed to have a shape similar to that of the die receiving area, and may also be provided with external pins, ball bumps or leads. A number of these "certain non-square" packages may be assembled in an electronic system on a mother board. Unpackaged "certain non-square" dies may be connected to the ends of traces on a substrate, and encapsulated to form a multi-chip module.
A patterned layer of conductive lines defining a die-receiving area for packaging a semiconductor die, comprising:
A patterned layer of conductive lines defining a die-receiving area for packaging a semiconductor die, comprising:
A patterned layer of conductive lines defining a die-receiving area for packaging a semiconductor die, comprising:
Dependencies are inferred from the claim text.