US 5,329,142 A · Self turn-off insulated-gate power semiconductor device with injection-enhanced transistor structure

Abstract

A self turn-off power semiconductor device includes a P type emitter layer, a high resistive N type base layer, a P type base layer and a MOS channel structure for injecting electrons into the N type base layer. A series of trench-like grooves are formed in the top surface of a substrate constituting the N type base layer at a constant interval. Insulated gate electrodes are buried in these grooves. The injection efficiency of electrons into the base layer is enhanced by locally controlling the flow of holes in the N type base layer. Controlling the flow of holes is achieved by specifically arranging the width of a hole-bypass path among the grooves, the trench width and the placement distance of the grooves, thereby causing the accumulation of carriers to increase in the base layer to decrease the on-resistance of the device.

Claims24

Dependent claims

A semiconductor device comprising:

a first semiconductive layer serving as a base layer with a trench defined therein having a wall;
a second semiconductive layer serving as a first current-carrying channel region connected to said base layer for allowing first type electrical carriers to be injected into said base layer;
a third semiconductive layer serving as a second current-carrying channel region allowing second type electrical carriers to be injected into said base layer mostly through the second channel region to cause a conduction modulation to occur therein;
a fourth semiconductive layer serving as a carrier drain layer causing carriers of said first type located in said base layer to move externally out of said base layer;
and
injection enhancer means for locally controlling a flow capability of the first type carriers in a portion of said base layer adjacent to the wall of said trench in order to thereby increase an ability to inject the second type carriers into said base layer.

3 more elements

A power semiconductor device comprising:

a lightly-doped semiconductive substrate which serves as a high-resistance base layer;
a plurality of insulate gate electrodes spaced at a predetermined interval in said substrate;
a first emitter layer of a first conductivity type in contact with said base layer for injecting first charge carriers of the first conductivity type into said base layer;
a second emitter layer of a second conductivity type having portions which are selectively arranged between said insulated gate electrodes in said substrate;
channel regions of first and second conductivity types defined in said base layer so that said channel regions are in contact with said base layer and said second emitter layer so as to face said insulated gate electrodes, said channel regions being induced by said insulated-gate electrodes to allow second charge carriers of the second conductivity type to be injected from said second emitter layer;
a semiconductive drain layer of the first conductivity type having portions which are selectively arranged between said insulated gate electrodes in said substrate to cause the first charge carriers to drain away to an external location;
said insulated gate electrodes being buried in a plurality of narrow and deep trench-like grooves and determined in size and placement distance to locally increase a resistivity to a flow of the first charge carriers in at least a portion of said base layer located between adjacent ones of said trench-like grooves, thereby accelerating injection of the second charge carriers into said base layer through said channel regions;
a first main electrode electrically coupled to said first emitter layer;
and
a second main electrode electrically coupled to said second emitter layer and said drain layer.

7 more elements

An insulated gate transmitter comprising:

a lightly-doped high-resistance semiconductive base layer of a first conductivity type having a surface;
a first semiconductive current-carrying layer of a second conductivity type coupled to said base layer;
a second semiconductive current-carrying layer of the second conductivity type coupled to said base layer;
a first main electrode electrically connected to said first current-carrying layer;
a second main electrode electrically connected to said second current-carrying layer;
a plurality of insulated gate electrodes buried in the surface of said base layer for injecting first and second type charge carriers through first and second type channels;
a semiconductive source layer of the first conductivity type having one or a plurality of portions facing said insulated gate electrodes in said base layer;
a semiconductive layer arranged between said insulated gate electrodes and said source layer, for defining a turn-off channel region at one or a plurality of portions thereof facing said insulated gate electrodes;
and
said insulated gate electrodes being buried in a plurality of narrow and deep trenches formed in said base layer to have a size and a distance which are so selected as to locally increase a bypass resistivity to a flow of first charge carriers of the first conductivity type injected from said first current-carrying layer in said base layer, thereby to enhance injection ability of second charge carriers of the second conductivity type into said base layer through said turn-off channel region.