Method of making high voltage PNP bipolar transistor in CMOS
AssigneeXerox Corporation
InventorsTuan A. Vo, Mohamad M. Mojaradi
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Abstract
A high voltage bipolar transistor fabricated on a CMOS substrate without adding any additional process steps. During the CMOS n-well mask and implant steps an n-well is formed for the transistor. Next, during the CMOS field and deep boron implant steps a circular p-field is formed within the n-well. Finally, during the CMOS p+ mask and implant steps the p+ emitter is formed. The presence of the p-field between the emitter and n+ base provides high voltage protection.
Claims2
The method of forming a high voltage bipolar transistor comprising an n-well, a p+ emitter and an n+ base at the surface of a p-type silicon substrate and located within said well, and a p-field at the surface of said substrate circularly surrounding said emitter and separating said emitter from said base, comprising the steps of:
- growing an oxide layer on the surface of said substrate,
- depositing a nitride layer on said oxide layer,
- using a first mask to etch away the nitride, to expose said oxide layer, except for two areas to form emitter and base nitride areas where the nitride remains,
- second masking to form an n-well exposed area overlapping and slightly larger than said emitter and base nitride areas,
- first implanting an n-well below said n-well area,
- third masking all of the surface of said substrate except for the area between said two nitride areas,
- second implanting in said area between said two nitride areas to form a p-field drift region to increase the breakdown voltage of the base to emitter junction,
- removing all of said nitride,
- fourth masking off all areas of said transistor except for said emitter area,
- third implanting to form a p+ emitter,
- fifth masking off all areas of said transistor except for said base area, and
- fourth implanting to form an n+ base.
The method of forming a high voltage bipolar transistor comprising a p- well, an n+ emitter and a p+ base at the surface of an n-type silicon substrate and located within said well, and an n-field at the surface of said substrate circularly surrounding said emitter and separating said emitter from said base, comprising the steps of:
- growing an oxide layer on the surface of said substrate,
- depositing a nitride layer on said oxide layer,
- using a first mask to etch away the nitride, to expose said oxide layer, except for two areas to form emitter and base nitride areas where the nitride remains,
- second masking to form a p-well exposed area overlapping and slightly larger than said emitter and base nitride areas,
- first implanting a p-well below said p-well area,
- third masking all of the surface of said substrate except for the area between said two nitride areas,
- second implanting in said area between said two nitride areas to form an n-field drift region to increase the breakdown voltage of the base to emitter junction,
- removing all of said nitride,
- fourth masking off all areas of said transistor except for said emitter area,
- third implanting to form an n+ emitter,
- fifth masking off all areas of said transistor except for said base area, and
- fourth implanting to form a p+ base.
Dependencies are inferred from the claim text.