Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right

A processor for collecting boolean conditions of multiple operations comprising:

• a multiple-bit condition collection register which, during and by processor operation, may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right;
• a processor instruction decoder structurally interconnected to said condition collection register for decoding an unmodified processor instruction set including a plurality of operand register addresses for reading source information from and writing operation result information to said condition collection register, wherein said processor instruction decoder decodes a first operand address as a read address for said condition collection register so as to read the source information from said condition collection register in parallel, a second operand address as a write address for said condition collection register so as to write the operation result information to said condition collection register in parallel, a third operand address as a write address for said condition collection register so as to serially shift operation result information into said condition collection register from the left, and a fourth operand address as a write address for said condition collection register so as to serially shift operation result information into said condition collection register from the right.