Multiprocessor system having local write cache within each data processor node

A multiprocessor data processing system, comprising:

• at least one group comprised of (n) computational nodes each of which includes a first data processor, each of the (n) computational nodes within said group being coupled together by a first local bus means;
• at least one communication node including a second data processor, the at least one communication node being coupled to data communication means by a second local bus means;
• at least one shared global memory comprised of (x) memory banks coupled together by a third local bus means;
• and
• a global bus means;
• a plurality of first bus interface means individual ones of which are coupled between one of said first, second, and third local bus means and said global bus means;
• a plurality of second bus interface means individual ones of which are coupled between one of said first and second local bus means and said data processors of said (n) computational nodes and said at least one communication node for receiving address and control signal lines therefrom, the control signal lines including a plurality byte enable signals that are generated by a data processor during a write cycle;
• wherein each of said computational and communication nodes is comprised of means for storing byte enable signals associated with one or more data processor write cycles;
• means for storing corresponding bytes of data written by the data processor during the one or more data processor write cycles;
• and means, responsive to stored byte enable signal indications, for asserting on the associated one of said first and second local bus means a global memory read-modify-write signal in response to a condition wherein, for a data unit comprised of a plurality of bytes, at least one associated byte enable signal is not asserted;
• and wherein said multiprocessor data processing system is further comprised of,
• means, coupled to said global bus means and to said at least one shared global memory, and responsive to an assertion of said read-modify-write signal, for reading data from a specified location within said at least one global memory, for selectively merging the data bytes to be written with the data read from the specified location in accordance with corresponding byte enable indications to form resultant data bytes, and for storing the resultant data bytes back into the specified location.

A method of operating a multiprocessor data processing system of a type having a plurality of processor nodes each of which includes a data processor, comprising the steps of:

• for each processor node, and for each data processor write to memory operation within a node that is directed to an addressable region of memory comprised of a predetermined number of contiguous bytes,
• buffering data written by the data processor to a first bus that is internal to the processor node;
• buffering byte enable signals generated by the data processor in conjunction with the data written by the data processor;
• and
• performing a main memory write operation by,
• transmitting the buffered data and the buffered byte enable signals to a second bus that couples together a plurality of the processor nodes;
• responsive to stored byte enable signals, also generating and transmitting a control signal to the second bus for specifying if the main memory write operation is to be accomplished as a read-modify-write type of memory operation or as a write type of memory operation;
• coupling the data, the control signal, and the byte enable signals from the second bus to a third bus for reception by the main memory;
• and
• responsive to the control signal specifying a read-modify-write type of memory operation,
• reading data from a specified location within the main memory, selectively merging the data from the third bus with the data read from the specified location, the data being selectively merged in accordance with the byte enable signals from the third bus, and storing a result of selectively merging the data back into the specified location.

A method of performing a memory write operation in a multiprocessor data processing system of a type having at least one processor node coupled to a local bus, the at least one node including a data processor, comprising the steps of:

• buffering, within the processor node, data and associated byte enable signals that are written by the associated data processor, said data processor being capable of generating a memory write command in conjunction with from one to N bytes of data to be written to the memory and from one to N corresponding byte enable signals;
• wherein the step of buffering buffers up to a total of M times N bytes of data from individual ones of a plurality of consecutively executed data processor memory write commands that are all directed to a same M times N byte address region within the memory, the step of buffering also buffering up to M times N of the associated byte enable signals;
• and
• performing the memory write operation by,
• determining, as a function of buffered byte enable signals, if the memory write operation should be accomplished as a read-modify-write (RMW) operation,
• if it is determined to accomplish the memory write operation as a RMW operation, transmitting the buffered data to the local bus in conjunction with the buffered byte enable signals and a RMW memory control signal;
• arbitrating for access to a global bus and, in response to receiving access to the global bus;
• coupling the data, the RMW control signal, and the byte enable signals from the local bus to the global bus for reception by a memory means;
• and
• the memory means being responsive to the RMW control signal for
• reading data from a specified location within the memory means, selectively merging the data from the global bus with the data read from the specified location in accordance with the byte enable signals, and storing a result of selectively merging the data back into the specified location.