Stage saving and restoring hardware mechanism

A general purpose register adapted for use in a CPU, comprising:

• a first memory device;
• an input section for transferring information from a data bus to said first memory device for storing said information;
• an output section for transferring said stored information from said first memory device to said data bus;
• a second memory device, connected to said first memory device, for capturing a copy of said information stored in said first memory device whenever the CPU detects an interrupt, said second memory device responsive to a save control signal that indicates when said information stored in said first memory device should be saved in said second memory device and a restore control signal that indicates when said first memory device should be restored with said copy of said information stored in said second memory device,
• wherein said information stored in said first memory device is saved in said second memory device and restored from said second memory device without accessing said data bus.

A method for performing state saving and restoring operations in a computer system having a central processor unit (CPU) with at least one data bus, at least one general purpose register, instruction decoding logic and a mechanism for detecting interrupt conditions, comprising the steps of:

• storing, without accessing the at least one data bus, the contents of the at least one general purpose register into at least one corresponding shadow register when the CPU issues a SAVE control signal upon the detection of an interrupt condition, said at least one corresponding shadow register is located substantially adjacent, and electrically connected to the at least one general purpose register;
• decoding a return from interrupt and restore (RFIR) instruction;
• generating a RESTORE control signal upon the decoding of the RFIR instruction;
• and
• transferring, without accessing said at least one data bus, the contents from said at least one corresponding shadow register back to be stored in the at least one general purpose register in response to the RESTORE control signal.