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US 5,327,564 AGranted
Timed access system for protecting data in a central processing unit
AssigneeDallas Semiconductor Corporation
InventorWendell L. Little
Life of this patent
Estimating the term…
Abstract
A system for protecting data in a CPU's internal register. To obtain write access to the protected register, a process must sequentially write first and second keywords to an access register, within a predetermined time window.
Claims7
A protection system for protecting internal data in a CPU, comprising:
- a protected internal register for storing the internal data without change except when accessed, said protected register having an enable input, and being configured to allow access thereto when an enable signal is received on said enable input;
- access register means for receiving and storing access data;
- compare means, connected to said access register means, for comparing said stored access data in said access register means with a predetermined access work and outputting a true compare signal if a match exists between said predetermined access word and said stored access data;
- and
- enable timing means, connected to said enable input of said protected register, for generating said enable signal for a predetermined amount of time when said true compare signal is detected on the output of said compare means such that said protected internal register is accessible only during said predetermined time after receipt of access data corresponding to said predetermined access word.
2 more elements
A circuit for protecting data in a register, comprising:
- a protected register which is sought to be protected against accidental overwriting;
- an access register, and a comparator connected to compare data stored in said access register with first or second predetermined access keywords and configured to output a compare signal accordingly;
- timed access logic, connected to receive said compare signal from said comparator, and connected to control access to said protected register;
- said protected register, said comparator, and said timed access logic being connected, together with at least one timing circuit, in a configuration such that said timed access logic allows access to said protected register only if said first predetermined keyword is written into said access register, AND thereafter said second predetermined keyword is written into said access register within a first predetermined maximum duration after said first predetermined keyword is written into said access register.
1 more element
Dependencies are inferred from the claim text.