Disabled memory sections for degraded operation of a vector supercomputer

A multiprocessing computer system for simultaneously running operating programs and diagnostic programs, comprising;

• memory means including multiple sections of memory having interleaved addresses for storing data at specified memory reference addresses within a contiguous address space across all of said sections;
• processor means including a plurality of processors for executing instructions and for storing said data in said memory means;
• failure detection means connected to said memory means and said processor means for detecting a hardware failure in said memory means;
• and
• address translation means operable in response to said failure detection means for translating said memory reference addresses to a first portion of said memory means into memory reference addresses to a second portion of said memory means.

A multiprocessing computer system for simultaneously running operating programs and diagnostic programs, comprising;

• memory means including multiple sections of memory having interleaved addresses for storing data at specified memory reference addresses within a contiguous address space across all of said sections;
• processor means including a plurality of central processors for executing instructions and for storing said data in said memory means;
• address control means for outputting said memory reference addresses;
• and
• maintenance workstation means through which an operator may control said address control means to force at least one of the address bits of all of said memory reference addresses from a selected central processor to a fixed value to force said selected central processor to access only a selected portion of all of said sections of said memory means.