US 5,327,541 A · Global rotation of data in synchronous vector processor

Abstract

An apparatus and method for performing rotation of data in a register file memory. The apparatus utilizes a rotation address generator including rotation value, modulus, and offset registers, a comparator, a data selector, logic circuitry, and a subtractor. A predetermined area (P.times.Q) of the register file memory and a rotation value corresponding to the number of bits to be rotated in the rotation area is designated by an instruction program memory. An instruction decoder signals the register file, modulus register, rotation value register, and offset register of an impending rotation of data, thereby enabling loading of the modulus and rotation value registers and resetting of the offset register. A counter provides a relative address to the comparator and data selector. The comparator compares the relative address with the output of the modulus register, determining whether selected ones of the addressed register file locations fall inside or outside of the rotation area, and send an appropriate signal to the logic circuitry, an OR gate. This OR gate also receives a rotate or not-rotate signal. Consequently, either an absolute address equal to (the value of the relative address-2 * the offset value) mod (8 * the value in the modulus register) or equal to the relative address, based on predetermined conditions, is utilized to access rotationally data from the register file.

Claims10

Dependent claims

A data processing system for rotation manipulation of data, said system including:

a register file for storing said data;
a global rotation address generator;
a register address counter;
an instruction program memory;
said counter providing a relative register address to said generator;
said generator providing said relative address to address register locations in said register file and including:
a rotation value register;
a modulus register;
an offset register;
a comparator;
a data selector (C);
an OR gate;
and
a subtractor (B);
said program memory defining a global rotation area and an input rotation value corresponding to an amount of said stored data for providing said rotation value and area to said rotation value register and modulus register, respectively;
an instruction decoder means for signaling said register file, modulus register, rotation value register and offset register of an impending global rotation, enabling loading of said rotation value and modulus registers by said program memory, and resetting said offset register;
said counter for providing said relative address to said comparator and said data selector-(C);
said comparator for comparing said relative address with output from said modulus register, determining whether selected ones of said address register file locations are outside said global rotation area, and sending a corresponding signal to said OR gate;
control bit means for sending a global rotate or not rotate signal to said OR gate;
said subtractor (B) for obtaining an absolute address by subtracting an offset value obtained from said offset register from a relative address value obtained from said counter;
where said absolute address may be utilized by a processor for accessing data rotationally from said register file.

18 more elements

A global rotation address generator for providing an absolute address for rotational addressing of stored data, said generator comprising:

a rotational value register for storing a rotational value corresponding to a total number of registers to be rotatably accessed;
a modulus register for storing a modulus value corresponding to a total global rotational memory area;
a first adder;
a first subtractor;
a first data selector;
an offset register;
said offset register storing an offset value and supplying said value to said first adder for adding to said rotational value, said first adder supplying an offset rotational value to said first subtractor and said first data selector;
said subtractor performing a left justified subtraction of said modulus value from said offset rotational value and supplying a result to said first data selector along with a sign indicator of said result;
said data selector sending said result to said offset register when said sign indicator is positive and otherwise sending said offset rotational value to said offset register;
a second subtractor;
a second adder;
a second data selector;
a comparator;
an OR gate;
and
a third data selector;
said second subtractor subtracting said offset value stored in said offset register from a relative address, said second subtractor passing a second result to said second adder and said second data selector and further sending a sign indicator of said second result to said second data selector, said second adder for receiving a left justified modulus value and adding said left justified modulus value to said second result, developing a second sum, and directing said second sum to said data selector;
said second data selector passing said second result when said sign indicator of said second result is positive and otherwise sending said second sum to said third data selector;
said comparator for receiving said left justified modulus value and comparing whether said left justified modulus value is greater than said relative address and if yes, sending no signal and otherwise sending a global rotation disabling signal to said OR gate;
said OR gate further for receiving a second global rotation disabling signal from an outside source, said OR gate logically testing for said global rotation disabling signal or said second global rotation disabling signal and passing a logical result to said third data selector where said logical result comprises a disabling signal when either said global rotation disabling signal or said second global rotation disabling signal is received;
said third data selector passing said relative address when said logical result comprises said disabling signal and otherwise passes a value received from said second data selector as an absolute address value.

18 more elements

A data processing system including:

an instruction program memory;
an address counter;
a global rotation address generator;
and an instruction decoder;
said instruction program memory sending a rotational value corresponding to a total number of registers to be rotated and a total global rotational memory area to said global rotation address generator;
said address counter providing a relative address to said global rotation address generator;
said instruction decoder sending load and operate signals to said global rotation address generator;
said global rotation address generator comprising:
a rotational value register for storing a rotational value corresponding to a total number of registers to be rotatably accessed;
a modulus register for storing a modulus value corresponding to a total global rotational memory area;
a first adder;
a first subtractor;
a first data selector;
an offset register;
said offset register storing an offset value and supplying said value to said first adder for adding to said rotational value, said first adder supplying an offset rotational value to said first subtractor and said first data selector;
said subtractor performing a left justified subtraction of said modulus value from said offset rotational value and supplying a result to said first data selector along with a sign indicator of said result;
said data selector sending said result to said offset register when said sign indicator is positive and otherwise sending said offset rotational value to said offset register;
a second subtractor;
a second adder;
a second data selector;
a comparator;
an OR gate;
and
a third data selector;
said second subtractor subtracting said offset value stored in said offset register from a relative address, said second subtractor passing a second result to said second adder and said second data selector and further sending a sign indicator of said second result to said second data selector, said second adder for receiving a left justified modulus value and adding said left justified modulus value to said second result, developing a second sum, and directing said second sum to said data selector;
said second data selector passing said second result when said sign indicator of said second result is positive and otherwise sending said second sum to said third data selector;
said comparator for receiving said left justified modulus value and comparing whether said left justified modulus value is greater than said relative address and if yes, sending no signal and otherwise sending a global rotation disabling signal to said OR gate;
said OR gate further for receiving a second global rotation disabling signal from an outside source, said OR gate logically testing for said global rotation disabling signal or said second global rotation disabling signal and passing a logical result to said third data selector where said logical result comprises a disabling signal when either said global rotation disabling signal or said second global rotation disabling signal is received;
said third data selector passing said relative address when said logical result comprises said disabling signal and otherwise passes a value received from said second data selector as an absolute address value.

26 more elements

Dependencies are inferred from the claim text.

Global rotation of data in synchronous vector processor

Life of this patent

Global rotation of data in synchronous vector processor

Life of this patent

Abstract

Claims10