Method and apparatus for decoding bus master arbitration levels to optimize memory transfers
AssigneeNCR Corporation
InventorsThomas F. Heil, Daniel C. Robbins, Edward A. McDonald
Life of this patent
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Abstract
A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.
Claims16
In a computer system including a plurality of bus masters connected through a common bus to a shared resource, and a data buffer interposed between said common bus and said shared resource, each one of said plurality of bus masters having a unique arbitration value associated therewith for prioritizing access to said shared resource through an arbitration process, the operation of said data buffer capable of being configured in accordance with different buffer configuration parameters, a method for optimizing data transmissions between said bus masters and said shared resource, comprising the steps of:
- storing buffer configuration parameters for each one of said plurality of bus masters within a register file, said buffer configuration parameters defining the optimal mode of buffer operation during data transmissions between each one of said plurality of bus masters and said shared resource;
- determining the arbitration value associated with the bus master granted access to said shared resource upon conclusion of said arbitration process;
- determining the bus master granted access to said shared resource by decoding the arbitration value associated with the bus master granted access to said shared resource:
- retrieving the buffer configuration parameters associated with said bus master granted access to said shared resource from said register file;
- and
- configuring said buffer to operate in accordance with said retrieved buffer configuration parameters.
A method for transferring data between one of a plurality of bus masters and a shared resource, each one of said plurality of bus masters being connected through a common bus and a data buffer to said shared resource and having a unique arbitration value associated therewith for prioritizing access to said common bus, through an arbitration process, comprising the steps of:
- determining the arbitration value associated with the bus master granted control of said common bus upon conclusion of said arbitration process;
- determining the bus master granted control of said common bus by decoding the arbitration value associated with the bus master granted control of said common bus;
- and
- configuring said data buffer for use with the bus master granted control of said common bus.
In a computer system including a plurality of bus masters connected through a common bus to a shared resource, and a data buffer interposed between said common bus and said shared resource, each one of said plurality of bus masters having a unique arbitration value associated therewith for prioritizing access to said shared resource through an arbitration process, the operation of said data buffer capable of being configured in accordance with different buffer configuration parameters, apparatus for optimizing data transmissions between said bus masters and said shared resource, the apparatus comprising:
- a register file for storing buffer configuration parameters for each one of said plurality of bus masters, said buffer configuration parameters defining the optimal mode of buffer operation during data transfers between each one of said plurality of bus masters and said shared resource;
- means for determining the arbitration value associated with the bus master granted access to said shared resource upon conclusion of said arbitration process;
- means for determining the bus master granted access to said shared resource by decoding the arbitration value associated with the bus master granted access to said shared resource;
- and
- means connected to said register file for retrieving the buffer configuration parameters associated with said bus master granted access to said shared resource from said register file;
- means connected to receive said retrieved buffer configuration parameters and connected to said data buffer for configuring said buffer to operate in accordance with said retrieved buffer configuration parameters.
An interface circuit connected between a plurality of bus masters and a shared resource for optimizing data transmissions between said bus masters and said shared resource, each one of said plurality of bus masters being connected through a common bus to said interface circuit and having a unique arbitration value associated therewith for prioritizing access to said common bus through an arbitration process, said interface circuit comprising:
- a variable configuration data buffer interposed between said common bus and said shared resource;
- and
- buffer control logic connected to receive the arbitration value associated with a bus master granted control of said bus upon the conclusion of said bus arbitration process and responsive thereto to configure said data buffer to buffer data transmissions between said controlling bus master and said shared resource.
Dependencies are inferred from the claim text.