Access processing system in information processor

An access processing system in an information processor, comprising:

• an accessed device provided with a memory means;
• an access deice for generating an access request signal for accessing said memory means according to a first access type;
• and
• an address bus and an access mode bus each connected to said access device and said accessed device, said access device generating the access request signal for an access to said memory means according to the first access type when less than all bit of said address bus are used for the access, said access device loading said access mode bus with mode data indicating the first access type and loading bits of said address bus, unused as address bits, with data including write data to be transferred to said accessed device, and when the mode data received by said accessed device from said access device through said access mode bus indicates the first access type, said accessed device reads predetermined bits of said address bus as address data and other bits of said address bus as the write data to access said memory means of said accessed device.