Method of utilizing common buses in a multiprocessor system
AssigneeCanon Kabushiki Kaisha
InventorsKazumasa Hamaguchi, Shigeki Shibayama
Life of this patent
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Abstract
In a multiprocessor system wherein a main storage is divided into a plurality of banks and a plurality of common buses are provided, in order to access the main storage. Each processor selects and acquires one of the buses in accordance with the utilization status of the common buses, and releases the bus after transmitting an access request utilizing the acquired bus. After processing the request, the main storage selects and acquires one of the buses in accordance with the utilization status of the common buses at that time independently of the bus which has transmitted the request, and transmits a result of the processing to the processor which has transmitted the access request utilizing the acquired bus.
Claims5
A method of utilizing common buses in a multiprocessor system where each of a plurality of common buses is connected to a plurality of processors and a plurality of shared memories, comprising the steps of:
- acquiring a first one of the plurality of common buses by one of the plurality of processors requesting access to one of the plurality of shared memories;
- transmitting the request to said one of the plurality of shared memories via the first acquired one of the plurality of common buses;
- releasing the first acquired one of the common buses by said one of the plurality of processors after transmitting said request without waiting for a reply therefor;
- processing said request by said one of the shared memories;
- acquiring a second one of the plurality of common buses independent of said first one by said one of the shared memories;
- and
- transmitting a result of the processing to said one of the plurality of processors via the second acquired one of the plurality of common buses.
A multiprocessor system, where each of a plurality of common buses is connected to a plurality of processors and a plurality of shared memories,
- each of said plurality of processors comprising:
- first acquiring means for acquiring a first one of the plurality of common buses;
- first transmission means for transmitting a request for access to said one of the plurality of shared memories via the first acquired one of the plurality of common buses;
- and
- releasing means for releasing the first acquired one of the common buses after transmitting said request without waiting for a reply therefor;
- each of the said plurality of shared memories comprising:
- processing means for processing a request for access from one of said plurality of processors;
- second acquiring means for acquiring a second one of the plurality of common buses independent of said first one;
- and
- second transmission means for transmitting a result of the processing to the one of the plurality of processors requesting the access via the second acquired one of the plurality of common buses.
Dependencies are inferred from the claim text.