Microprocessor having branch prediction function

Abstract

A microprocessor which prefetches instructions in words which contain a fixed plurality of bytes based on addresses which disregard one or more less significant bits and in which instructions comprises a variable number of bytes includes an adder for supplying information regarding the starting location for each instruction within a multi-byte, prefetched word held in a queue for alignment of the instruction for decoding by an instruction decoder. Upon the occurrence of an unconditional branch instruction or a conditional branch instruction in which the condition is met, a multiplexer is used to substitute a starting location stored in a branch hit table for the branch target instruction within a multi-byte, prefetched word for the starting for the starting location developed by the adder. Prefetching is performed by incrementing addresses by a number corresponding to the number of less significant bits disregarded in the addresses and accessing a branch prediction table and also the branch hit table when a branching instruction is encountered. An acknowledgement of a prefetch is then used to serialize prefetching of the word containing the start location of the branch target. If the branch target is also a branch instruction, this serialization allows repetition of the prefetch through a number of branching instructions limited only by the capacity of the branch hit table and disturbance of pipelined processing is thereby reduced.

Dependencies are inferred from the claim text.