# US 5,327,466 A · 1X asynchronous data sampling clock

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- Number: US 5,327,466 A
- Document ID: US5327466A
- Status: Granted
- Kind: A
- Application number: 07/750,968
- Filed: 1991-08-28
- Granted: 1994-07-05
- Earliest claimed: 1991-08-28
- Inventors: Frank Marinaro
- Web page: https://patentgrep.com/patent/US5327466A

## CPC

- H04L 7/0338: {the correction of the phase error being performed by a feed forward loop}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A circuit for retiming asynchronous data. A sampling clock is derived in which the system clock frequencies are no higher than that of the data frequency. The leading edge of the signal from a received data-to-clock position circuit and a bias distortion circuit are combined and decoded to determine the center of the received data to select the proper sampling clock for the received data.

## Claims

### Claim 1

A received data sampling clock circuit for use in asynchronous local area networks, comprising a RD (received data)-to-clock position circuit for determining the position of RD with respect to a system clock; a bias distortion circuit for determining the pulse width of the RD; and means for combining and decoding output signals from said RD-to-clock position circuit and said bias distortion circuit for determining an approximate center of said RD and for selecting a proper sampling clock for said RD.

### Claim 2 (depends on 1)

The received data sampling clock circuit of claim 1, said RD-to-clock position circuit comprising a multitapped delay line, an input of said delay line being a system clock; and means for latching delay line outputs from said multitapped delay line, said latching means including a first D-Type Data Latch and utilizing a leading edge of the RD input signal to determine a delayed clocks-to-RD phase relationship.

### Claim 3 (depends on 2)

The received data sampling clock circuit of claim 2, said means for combining and decoding output signals and selecting a proper sampling clock comprising at least a ROM having at least one input connected to said bias distortion circuit and at least one input connected to said RD-to-clock position circuit and at least one output connected to at least one input of a data selector multiplexer, said data selector multiplexer having at least one input connected to said RD-to-clock position circuit and an output of said data selector multiplexer being said sampling clock.

### Claim 4 (depends on 3)

The received data sampling clock circuit of claim 3, in which said delay line outputs of said multitapped delay line are connected to data inputs of said data selector multiplexer to provide a plurality of clock positions.

### Claim 5 (depends on 4)

The received data sampling clock circuit of claim 4, in which said delay line outputs of said multitapped delay line are also connected to D inputs of said first D-Type Data Latch so as to allow the phase of said delay line outputs to be latched into said first D-Type Data Latch by the leading edge of the RD input signal.

### Claim 6 (depends on 3)

The received data sampling clock circuit of claim 3, in which the outputs of the delay line are connected to the data inputs of said data selector multiplexer.

### Claim 7 (depends on 3)

The received data sampling clock circuit of claim 3, said means for latching said delay line outputs comprising two AND gates and a D-Type flip-flop, a first AND gate having at least one input connected to an output of said D-Type flip-flop and the other input connected to one of said ROM outputs and being used to enable a second AND gate, and said second AND gate having one input connected to the RD input signal and another input connected to an output of said first AND gate and said second AND gate having an output connected to a clock input of said first D-Type Data Latch for latching said delay line outputs into said first D-Type Data Latch.

### Claim 8 (depends on 7)

The received data sampling clock circuit of claim 7, said one of said ROM outputs being high only if bias distortion of said RD input signal is within a predetermined range.

### Claim 9 (depends on 7)

The received data sampling clock circuit of claim 7, in which the first D-Type Data Latch outputs are connected to address inputs of the ROM.

### Claim 10 (depends on 7)

The received data sampling clock circuit of claim 7, in which the outputs of said ROM are connected to the address inputs of the data selector multiplexer.

### Claim 11 (depends on 1)

The received data sampling clock circuit of claim 1, said bias distortion circuit comprising a delay line, an input of which is the RD input signal; a second D-Type Data Latch for latching at least one output of said delay line; means for latching the delay line outputs into said second D-Type Data Latch with a trailing edge of the RD input signal for determining the position of the RD; and a Priority Encoder responsive to the latched delay line outputs to determine RD bias distortion.

### Claim 12 (depends on 11)

The received data sampling clock circuit of claim 11, the latching means further comprising an AND gate having one input connected to an output of said Priority Encoder and another input connected to an output of said delay line, a NOR gate having one input connected to an output of said AND gate and another input connected to a reset signal, a D-Type flip-flop having an enable input connected to an output of said NOR gate, and a NAND gate having one input connected to an output of said D-Type flip-flop, another input connected to said RD input signal and an output connected to said second D-Type Data Latch.

### Claim 13 (depends on 12)

The received data sampling clock circuit of claim 12, in which a high to low transition caused by the trailing edge of the RD input signal results in a low to high transition on the output of the NAND gate; said low to high transition at the NAND gate output latching the outputs of the delay line into said second D-Type Data Latch.

### Claim 14 (depends on 13)

The received data sampling clock circuit of claim 13, in which the outputs of said second D-Type Data Latch are connected to priority inputs of said Priority Encoder.

### Claim 15 (depends on 14)

The received data sampling clock circuit of claim 14, in which the outputs of the Priority Encoder are connected to address inputs of the ROM.

### Claim 16 (depends on 15)

The received data sampling clock circuit of claim 15, in which the latched information of the leading edge of the RD input signal and the bias distortion circuit outputs are combined and decoded as address inputs of a ROM that has been programmed to compensate for component internal delays to define a delayed clock.

### Claim 17 (depends on 16)

The received data sampling clock circuit of claim 16, in which said ROM outputs are connected to the address inputs of said data selector multiplexer.

### Claim 18 (depends on 17)

The received data sampling clock circuit of claim 17, in which the delayed clock selected by the ROM address inputs to the data selector multiplexer is the sampling clock for the RD input signal and appears at the center of the RD input signal.

### Claim 19

A method for receiving and retiming asynchronous data, comprising:
transferring received data to an RD-to-clock position circuit to determine a delayed clock-to-RD phase relationship;
compensating for bias distortion associated with said received data by providing a bias distortion circuit; and
combining and decoding outputs from said RD-to-clock position circuit and said bias distortion circuit to determine a true center of said received data and to select a proper sampling clock for said received data.