Frame alignment circuit

A frame alignment circuit comprising:

• a first series-to-parallel data converting means including:
• a first shift register for receiving a clock signal and a series data signal, accumulating the series data signal and outputting an accumulated series data signal;
• a first latch circuit for receiving the accumulated series data signal and a divided clock signal, converting the accumulated series data signal into a first parallel data signal and outputting the parallel data signal;
• and
• a first counter for receiving the clock signal, dividing the clock signal into the divided clock signal and outputting the divided clock signal;
• a second series-to-parallel data converting means including:
• a second shift register for receiving the parallel data signal and the divided clock signal, accumulating the parallel data signal and outputting an accumulated parallel data signal;
• a second latch circuit for receiving the accumulated parallel data signal and a second divided clock signal, further converting the accumulated parallel data signal into a second parallel data signal and outputting an accumulated second parallel data signal;
• and
• a second counter for receiving the divided clock signal and a shifting signal, further dividing the divided clock signal and outputting the second divided clock signal;
• pattern detecting means for receiving said accumulated second parallel data signal, detecting frame alignment pattern and outputting a frame alignment pattern detection result signal;
• a frame alignment determining means for receiving said frame alignment pattern detection result signal, detecting a deviation of alignment of the frame alignment pattern and outputting a deviation of alignment signal;
• a shift controlling means for receiving the deviation of alignment signal and the frame alignment pattern detection result signal, for expanding the deviation of alignment signal and outputting the shifting signal;
• and
• wherein the second counter, in response to the shifting signal, shifts an order of the second parallel data signal.