Timing and control circuit for a static RAM responsive to an address transition pulse

Abstract

An SRAM having an input address bus, a memory array and coupled sense amplifiers, internal sense amp enable and output data bus enable nodes further includes a circuit for generating an asynchronous address transition signal from a series of address signals received on the input address bus, and a timing and control circuit. The timing and control circuit selects a single address signal and suppresses the other address signals within a predetermined period of time such as the normal cycle time of the SRAM. If the address transition signal includes a pulse train of two or more pulses spaced apart by less than the predetermined time interval, the timing and control circuit generates fixed pulse width sense amp enable and output data bus enable signals corresponding to the last pulse in the pulse train. If the pulses are spaced apart by more than the predetermined time interval, the timing and control circuit generates fixed pulse width sense amp enable and output data bus enable signals corresponding to each pulse in the pulse train of the address transition signal. If the address transition signal is a single pulse having a variable pulse width related to the number of different address signals received on the address bus, the timing and control circuit generates fixed pulse width sense amp enable and output data bus enable signals corresponding to the single pulse of the address transition signal.

Dependencies are inferred from the claim text.