External memory interface circuit capable of carrying out initialization of external memory with a reduced initialization time duration

An external memory interface circuit included in a signal processing circuit which is for processing an input signal by using an external memory connected to said signal processing circuit, said signal processing circuit comprising clear signal generating means for generating a clear signal designating initialization of said external memory, said external memory interface circuit being connected to said clear signal generating means and comprising an address register for producing an address signal representing an address of said external memory at a time to supply said address signal to said external memory and a write-in register for writing said input signal in said external memory, said external memory interface circuit carrying out said initialization of said external memory on reception of said clear signal and further comprising:

• end address detecting means connected to said address register for detecting an end address of said address signal to produce an end address detection signal;
• signal generating means connected to said clear signal generating means and said end address detecting means for continuously generating an enable signal, a write-in pulse signal, and an address increment pulse signal until said signal generating means receives said end address detection signal after reception of said clear signal, said signal generating means supplying said enable signal, said write-in pulse signal, and said address increment pulse signal to said write-in register, said external memory, and said address register, respectively;
• and
• reset signal generating means connected to said signal generating means for generating an address reset signal on reception of said enable signal to supply said address reset signal to said address register;
• said write-in register successively producing zero data while said write-in register receives said enable signal to successively write said zero data in said external memory in synchronism with said write-in pulse signal, said address register producing address zero on reception of said address reset signal and increasing said address of said external memory one by one in response to said address increment pulse signal.