Semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise

A semiconductor integrated circuit comprising:

• a plurality of memory blocks, each of the memory blocks having a plurality of memory cells, and each of the memory cells storing data in response to a write enable signal at ground potential;
• control means for generating a control signal set at a power source potential when the memory blocks store data;
• a plurality of first wirings for supplying the control signal generated by the control means to the memory blocks;
• a plurality of inverting means, each of the inverting means being located near and corresponding to a respective one of the memory blocks, for inverting control signals supplied to the memory blocks by the plurality of first wirings, thereby generating write enable signals;
• and
• a plurality of second wirings for supplying the write enable signals generated by the inverting means to the memory blocks, each of the second wirings being shorter than a portion of each of the first wirings coupled between the control means and the inverting means, wherein each of the inverting means includes:
• a first inverter for inverting the control signal applied to the memory blocks by the plurality of first wirings,
• a first transfer gate couple between a first node and an output of the first inverter,
• a first depletion-type MOS transistor having a source and a drain coupled to the first node, and a gate coupled to a power-source potential terminal, the first depletion-type MOS transistor functioning as a first capacitor,
• a second inverter for inverting a signal at the first node,
• a second transfer gate coupled between a second node and an output of the second inverter, a second depletion-type MOS transistor having a source and a drain coupled to a ground-potential terminal, and a gate coupled to the second node, the second depletion-type MOS transistor functioning as a second capacitor, and
• a NAND gate for generating a logic NAND of a signal at the second node and the control signal, thereby generating a write enable signal.