Double buffer type elastic store comprising a pair of data memory blocks

A double buffer type elastic store supplied with a sequence of reception data, a sequence of reception clock pulses of a predetermined clock period, a sequence of reception frame pulses comprising successive reception frames each of which has a predetermined frame period, a sequence of system clock pulses of said predetermined clock period, and a sequence of system frame pulses comprising successive system frames each of which has said predetermined frame period and a system frame phase for producing a sequence of output data synchronized with said system frame phase within a predetermined phase difference, said sequence of reception clock pulses and said sequence of reception frame pulses being propagated through a time division transmission path, said elastic store comprising:

• a first memory block which receives said sequence of reception data and memorizes said sequence of reception data as first memorized data;
• a second memory block which receives said sequence of reception data and memorizes said sequence of reception data as second memorized data;
• a first signal generating circuit supplied with said sequence of reception clock pulses and said sequence of reception frame pulses for alternately generating first and second write-in reset signals on reception of each of said reception frame pulses to alternately supply said first and said second write-in reset signals to said first and said second memory blocks, respectively, and generating an indication signal indicative of one of said first and said second memory blocks that is supplied with either said first or said second write-in reset signal, said first and said second memory blocks alternately memorizing said sequence of reception data every other frame in response to said first and said second write-in reset signals, respectively;
• a second signal generating circuit supplied with said sequence of system clock pulses, said sequence of system frame pulses, and said indication signal for alternately generating first and second read-out reset signals on reception of each of said system frame pulses to alternately supply said first and said second read-out reset signals to said first and said second memory blocks, respectively, and generating a selection signal indicative of one of said first and said second memory blocks that is supplied with either said first or said second read-out reset signal, said first and said second memory blocks alternately delivering said first and said second memorized data every other frame, as first and second read-out data, in response to said first and said second read-out reset signals, respectively;
• and
• a selector connected to said first and said second memory blocks for selecting one of said first and said second read-out data as selected read-out data in response to said selection signal to produce said selected read-out data as said sequence of output data.