Dynamic random access memory having an improved operational stability

A dynamic random access memory, comprising:

• a plurality of memory cells each storing information in the form of electric charges, said memory cells being arranged to form a memory cell array;
• addressing means supplied with address data for selecting a memory cell from said memory cell array;
• input/output means for writing and/or reading information to and from said selected memory cell;
• and
• control means for controlling said input/output means such that said input/output means exhibits a high impedance state during a refreshing cycle of said memory cells, said control means comprising:
• first input means supplied with a first timing signal for outputting a first control signal in response thereto;
• second input means supplied with a second, different timing signal for outputting a second control signal in response thereto, said first timing signal and said second timing signal having a timing relationship such that a read/write cycle for writing and reading information to and from the selected memory cell is achieved when said first timing signal precedes said second timing signal and such that a refreshing cycle for refreshing said memory cells is achieved when said second timing signal precedes said first timing signal;
• a timing control circuit supplied with said first and second control signals from said first and second input means, respectively, for producing a third control signal in response thereto such that said third control signal is produced in response to a leading edge of said second control signal and terminates in response to a trailing edge of said second control signal when in said read/write cycle and such that said third control signal is produced in response to a leading edge of said first control signal and terminates in response to a trailing edge of said second control signal when in said refreshing cycle;
• a detection circuit supplied with said first and second control signals from said first and second input means, respectively, for producing a fourth control signal when the timing of said second control signal has preceded the timing of said first control signal, thereby corresponding to said refreshing cycle;
• a refresh control circuit supplied with said third control signal from said timing control circuit and said fourth control signal from said detection circuit for producing a fifth control signal such that said fifth control signal is produced in correspondence to a time interval extending from a time corresponding to the leading edge of said fourth control signal to a time corresponding to the trailing edge of said third control signal;
• an output control circuit supplied with said third control signal from said timing control circuit and with said fifth control signal from said refresh control circuit, for producing sixth and seventh control signals such that said sixth control signal is produced only in said read/write cycle, in correspondence to an interval extending from a time corresponding to the leading edge of said third control signal to a time corresponding to the trailing edge of said third control signal and such that said seventh control signal is produced in said read/write cycle in correspondence to an interval extending from a time corresponding to the leading edge of said third control signal to a time corresponding to the trailing edge of said third control signal, said seventh control signal produced in said refreshing cycle in an interval extending from a time corresponding to the leading edge of said third control signal to a time corresponding to the trailing edge of said third control signal, wherein said seventh control signal does not overlap said sixth control signal during said refresh cycle;
• said output control circuit controlling said input/output means by said sixth and seventh control signals such that reading and/or writing of information to and from a selected memory cell is allowed only when said sixth and seventh control signals are provided simultaneously, said output control circuit further controlling said input/output means such that said input/output means exhibits a high output impedance state when said seventh control signal is not provided.