Dual port semiconductor memory device with high speed data transfer during reading and writing modes

A semiconductor memory device comprising:

• a first memory array having a plurality of first memory cells arranged in a plurality of columns,
• a second memory array for temporarily storing a readout data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns,
• wherein each second memory cell includes
• a first node,
• a second node,
• first inverting means for inverting the potential of said first node to provide the same to said second node,
• second inverting means for inverting the potential of said second node to provide the same to said first node, the drive capability of said first inverting means being greater than that of said second inverting means,
• data bus means for receiving both a data signal readout from said second memory cell and an externally applied data signal,
• readout means for reading out a data signal from one of said plurality of first memory cells,
• amplifying means for sensing and amplifying both a data signal readout by said readout means and a data signal temporarily stored in said each second memory cell,
• first connecting means for electrically connecting each first node to said amplifying means at the time of data reading and data writing,
• second connecting means for electrically connecting and disconnecting said each second node to and from said data bus means during data reading and data writing, respectively,
• third connecting means for electrically connecting and disconnecting said each first node to and from said data bus means during data writing and data reading respectively, and
• first and second control signal generating means generating control signals for controlling said second and third connecting means,
• said first control signal generating means generating a first control signal for controlling the second connecting means to connect the second node to said data bus means during data reading and to isolate the second node from said data bus during data writing,
• said second control signal generating means generating a second control signal for controlling the third connecting means to connect the first node to said data bus means during data writing and to isolate the first node from said data bus means during data reading.

A method of operating a semiconductor memory device comprising:

• a first memory array having a plurality of first memory cells arranged in a plurality of columns,
• a second memory array for temporarily storing a read out data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns,
• wherein each second memory cell includes first and second mutually complementary storage nodes,
• data bus means for receiving a data signal read out from said second memory cell and an externally applied data signal,
• read out means for reading out a data signal from one of said plurality of first memory cells,
• amplifying means for sensing and amplifying both a data signal read out by said read out means and a data signal temporarily stored in each of said second memory cell,
• the method comprising the steps of:
• electrically connecting each first node to said amplifying means during data reading and data writing,
• electrically connecting each second node to said data bus means during data reading and electrically isolating said each second node from said data bus means during data writing, and
• electrically connecting said each first node to said data bus means during data writing and electrically isolating said each first node from data bus means during data reading.

A semiconductor memory device comprising:

• a first memory array having a plurality of first memory cells arranged in a plurality of columns;
• a second memory array for temporarily storing a read out data signal from said first memory array and a write data signal to be written into said first memory array, said second memory array including a plurality of second memory cells provided corresponding to said plurality of columns,
• wherein each of said second memory cells includes
• first and second complementary storage nodes,
• bidirectional inverting means interconnecting said first and second storage nodes,
• means for limiting magnitude of current flow within said inverting means in one direction to be less than that within said inverting means in the opposite direction,
• data bus means for receiving a data signal read out from said second memory cell and an externally applied data signal,
• read out means for reading out a data signal from one of said plurality of first memory cells,
• sense amplifier means for sensing and amplifying a data signal read out by said read out means and a data signal temporarily stored in each second memory cell,
• first connecting means for electrically connecting one node of said complementary storage nodes to said sense amplifier means at the time of data reading and data writing,
• second connecting means, for electrically connecting and disconnecting the other one of said complementary storage nodes to and from said data bus means during data reading and data writing, respectively,
• third connecting means for electrically connecting and disconnecting said one node to and from said data bus means during data writing and data reading, respectively,
• first and second control signal generating means for generating control signals for controlling said second and third connecting means,
• said first control signal generating means generating a first control signal for controlling the second connecting means to connect said other node to said data bus means during data reading and to isolate said other node from said data bus during data writing,
• said second control signal generating means generating a second control signal for controlling the third connecting means to connect said one node to said data bus means during data writing and to isolate said one node from said data bus means during data reading.