Method of erasure for a non-volatile semiconductor memory device

A method of erasure for a non-volatile semiconductor memory device having a floating gate, said method comprising the steps of:

• applying a first voltage having one polarity to a control gate of said memory device under a bias application between source and drain regions so as to accomplish an erasure by a tunneling of carriers from said floating gate through a tunneling oxide film;
• applying a second voltage having an opposite polarity to said one polarity to said control gate of said memory device without bias application between said source and drain regions so as to accomplish a convergence of a threshold voltage into a voltage level by a tunneling of carriers from a channel region of said memory device to said floating gate through said tunneling oxide film;
• and
• applying a third voltage having an opposite polarity to said voltage polarity of said second voltage application to a substrate during said second voltage application.