US 5,327,383 AGranted

Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy

AssigneeIntel Corporation

InventorsAmit Merchant, Mickey L. Fandrich, Neal Mielke

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Abstract

Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure. The circuitry also includes a postcondition controller and a program controller.

Claims34

Dependent claims

Circuitry for controlling the erasure of a nonvolatile semiconductor memory array including a multiplicity of rows of memory cells, each memory cell having a threshold voltage, the circuitry residing on a same substrate as the nonvolatile semiconductor memory array, the circuitry comprising:

a) a sequencer circuit for controlling the sequence of preconditioning and erasure of the nonvolatile semiconductor memory in response to an erase command, the sequencer circuit bringing a precondition enable signal active in response to the erase command, the sequencer circuit bringing an erase enable signal active in response to a precondition status signal:
b) a precondition controller for controlling the preconditioning of the nonvolatile semiconductor memory array, the precondition controller initiating preconditioning of the nonvolatile semiconductor memory array in response to the active precondition enable signal, the precondition controller generating the precondition status signal after the nonvolatile semiconductor memory array has been preconditioned, the precondition controller causing the threshold voltages of the memory cells to be raised to a level sufficient to prevent overerasure;
and
c) an erase controller for controlling the erasure of the nonvolatile semiconductor memory array, the erase controller initiating erasure of the nonvolatile semiconductor memory array in response to the active erase enable signal, the erase controller causing the threshold voltages of the memory cells to be brought to a level representative of an erased state.

1 more element

Circuitry for controlling the erasure of a nonvolatile semiconductor memory array including rows of memory cells and a pair of rows shorted together, each memory cell having a threshold voltage, the circuitry residing on a same substrate as the nonvolatile semiconductor memory array, the circuitry comprising:

a) a pair of redundant rows for replacing the pair of rows shorted together;
b) a sequencer circuit for controlling the sequence of preconditioning and erasing the nonvolatile semiconductor memory array, the sequencer circuit bringing a precondition enable signal active in response to an erase command, the sequencer circuit bringing an erase enable signal active in response to a precondition status signal;
c) a precondition controller for controlling the preconditioning of the nonvolatile semiconductor memory array, preconditioning causing the threshold voltages of the memory cells to be brought to a level sufficient to prevent overerasure, the precondition controller initiating preconditioning in response to the active precondition enable signal, the precondition controller bringing active the precondition status signal after preconditioning of the nonvolatile semiconductor memory array;
and
d) an erase controller for controlling the erasure of the nonvolatile semiconductor memory array, the erase controller initiating erasure in response to the active erase enable signal, the erase controller causing the threshold voltages of the memory cells to be brought to a level representative of an erased state.

2 more elements

Circuitry for controlling the erasure and programming of a nonvolatile semiconductor memory array including rows of memory cells and a pair of rows shorted together, each memory cell having a threshold voltage, the circuitry residing on a same substrate as the nonvolatile semiconductor memory array, the circuitry comprising:

a) a pair of redundant rows for replacing the pair of rows shorted together;
b) a program controller for controlling the programming of the nonvolatile semiconductor memory array in response to a program command, the program controller replacing the pair of shorted rows with the pair of redundant rows during programming;
c) a sequencer circuit for controlling the sequence of preconditioning and erasure the nonvolatile semiconductor memory array, the sequencer circuit bringing a precondition enable signal active in response to an erase command, the sequencer circuit bringing an erase enable signal active in response to a precondition status signal;
d) a precondition controller for controlling the preconditioning of the nonvolatile semiconductor memory array and the pair of rows shorted together by disabling their replacement with the pair of reduntant rows, preconditioning causing the threshold voltages of the memory cells to be brought to be raised to a level sufficient to prevent overerasure, the precondition controller initiating preconditioning in response to the active precondition enable signal, the precondition controller bringing active the precondition status signal after preconditioning of the nonvolatile semiconductor memory array;
and
e) an erase controller for controlling the erasure of the pair of redundant rows, the nonvolatile semiconductor memory array and the pair of rows shorted together, the erase controller initiating erasure in response to the active erase enable signal, the erase controller causing the threshold voltages of the memory cells to be brought to a level representative of an erased state.

3 more elements

Dependencies are inferred from the claim text.