Current offset sense amplifier of a modulated current or current unbalance type for programmable memories

A method for reading the information stored in a cell of a programmable memory matrix comprising:

• using a pair of NOR gates to drive a pair of pass transistors, the first pass transistor connecting a selected matrix bit line to a matrix bit line sense node of a differential amplifying stage, the second pass transistor connecting a reference line to a reference line sense node of the differential amplifying stage;
• comparing the conductivity of the selected matrix bit line containing said cell and the conductivity of the reference line containing a reference cell of a known state which comprises forcing a current of a predetermined level through each of said lines and through a load functionally connected to each line for converting a differential current signal into a voltage difference;
• amplifying said voltage difference by means of the differential amplifying stage, for producing a logic voltage difference between two output nodes representative of the state of said cell;
• and
• storing the extracted information in an output latch by utilizing two equal loads connected to said lines and cross-coupled thereto to form together with a differential input pair of transistors of a differential amplifying stage an output storage latch for storing the extracted information.

A method for reading the information stored in a cell of a programmable memory matrix comprising:

• comparing the conductivity of a selected matrix bit line containing said cell and the conductivity of a reference line containing a reference cell of a known state which comprises forcing a current of a predetermined level through each of said lines and through a load functionally connected to each line for converting a differential current signal into a voltage difference;
• amplifying said voltage difference by means of a differential amplifying state, for producing a logic voltage difference between two output nodes representative of the state of said cell;
• storing the extracted information in an output latch by utilizing two equal loads connected to said lines and cross-coupled thereto to form together with a differential input pair of transistors of a differential amplifying stage an output storage latch for storing the extracted information;
• switching a first clock signal low to precharge a pair of sense nodes to a selected voltage, wherein the first sense node functionally connects the matrix bit line to the amplifying stage and the second sense node functionally connects the reference line to the amplifying stage;
• maintaining said first clock signal low until said sense nodes reach a stable voltage;
• switching a second clock signal low to initiate a discrimination phase to produce a relatively small potential difference between a reference node and a storage node;
• switching a third clock signal high to initiate an evaluation phase that rapidly amplifies the small difference of the discrimination phase into a large difference;
• and
• switching said first clock signal to high to drive the output signal completely to either Vcc or ground, depending on the state of the read data, and placing the sense amplifier in a zero power consumption state.

A sense amplifier comprising:

• a memory bit line sense node and a reference bit line sense node;
• two cross coupled differential transistors having the gate of a first one coupled to the memory bit line sense node and the drain of a second one coupled to the memory bit line sense node and having the gate of the second coupled to the reference bit line sense node and the drain of the first coupled to the reference bit line sense node;
• two identical load transistors, coupled between a selected voltage potential and the memory bit line sense node and the reference bit line sense node, respectively, and their respective gates cross-coupled to the respective reference bit line sense node and the memory bit line sense node, respectively,
• a first clocked transistor connecting the gates of the two identical loads to each other when the clocked transistor is clocked to be conductive and disconnecting the gates of the identical load transistors from each other when the first clocked transistor is clocked to be non-conductive;
• and
• a second clocked transistor connecting a memory bit line to a reference bit line when the second clocked transistor is clocked to be conductive and disconnecting the memory bit line when the second clocked transistor is clocked to be non-conductive
• a third clocked transistor connecting the sources of the cross-coupled differential transistors to a reference potential when the third clocked transistor is clocked to be conductive, the first clocked transistor, second clocked transistor, and the third clocked transistor each being clocked by respective first, second, and third clocking signals.

A sense amplifier comprising:

• a memory bit line and a reference bit line having a memory bit line sense node and a reference bit line sense node respectively;
• two cross coupled differential transistors having the gate of a first one coupled to the memory bit line sense node and the drain of a second one coupled to the memory bit line sense node and having the gate of the second coupled to the reference bit line sense node and the drain of the first coupled to the reference bit line sense node;
• two identical load transistors, coupled between a selected voltage potential and the memory bit line sense node and the reference bit line sense node, respectively, and their respective gates cross-coupled to the respective reference bit line sense node and the memory bit line sense node, respectively;
• a clocked transistor connecting the gates of the two identical loads to each other when the clocked transistor is clocked to be conductive and disconnecting the gates of the identical load transistors from each other when it is clocked to be nonconductive;
• a pair of pass transistors, one each coupled between the memory bit line and the memory bit line sense node and the reference bit line and reference bit line sense node;
• and
• a pair of NOR gates each having one of their inputs clocked and the other input connected to the memory bit line and the reference bit line, respectively, and each having their outputs connected to the gate of the respective one of the pair of the pass transistors, respectively.